Nigel Topham

Search results

• 2008

  Translating a simulation-target memory access to a simulation-host memory access

  Topham, N. P., 1 May 2008, Patent No. WO 2008053160 A1

  Research output: Patent

  • Simulation 100%
  • Computer Systems 81%
  • Plurality 36%
• 2007

  Systolic-array based systems and methods for performing block matching in motion compensation

  Topham, N., 1 Mar 2007, Patent No. US 20070071101 A1

  Research output: Patent

  • Systolic arrays 100%
  • Motion compensation 92%
  • Pixels 58%

• Architecture for microprocessor-based systems including simd processing unit and associated systems and methods

  Wong, K-L., Graham, C., Topham, N., Jones, S., Aristodemou, A., Nemouchi, Y. & Lim, S. C., 2007, IPC No. WO 2007049150, Priority date 28 Sep 2005

  Research output: Patent

  • Microprocessor chips 100%
  • Systolic arrays 71%
  • Engines 71%
  • Interpolation 47%
  • Pixels 41%

• Parameterizable clip instruction and method of performing a clip operation using the same

  Topham, N., Nemouchi, Y., Jones, S., Graham, C., Wong, K-L. & Aristodemou, A., 2007, Patent No. 20070074007, Priority date 28 Sep 2005

  Research output: Patent

  • microprocessors 100%
  • methodology 21%
• 2006

  Processor Adapted to Receive Different Instruction Sets

  Topham, N., 2006, Patent No. US patent no. 7,130,989

  Research output: Patent

• Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions

  Topham, N., 2006, Patent No. US patent no. 7,124,279

  Research output: Patent

• Stall Control

  Topham, N., 2006, Patent No. US patent no. 6,993,641

  Research output: Patent

• 2005

  Barrel shifter for a microprocessor

  Wong, K. L. & Topham, N., 1 Dec 2005, Patent No. US 20050289323 A1

  Research output: Patent

  • Microprocessor chips 100%

• Systems and methods for performing branch prediction in a variable length instruction set microprocessor

  Wong, K. L., Hakewill, J., Topham, N. & Fuhler, R., 1 Dec 2005, Patent No. US 20050278517 A1

  Research output: Patent

  • Microprocessor chips 100%
  • Set theory 71%
  • Clocks 10%
  • Data storage equipment 7%

• Early resolving instructions

  Joyce, N. & Topham, N., 1 Feb 2005, Patent No. US 20050033941 A1

  Research output: Patent

• Predicated Execution of Instructions in Processors

  Topham, N., 2005, Patent No. US patent no. 6,944,853

  Research output: Patent

• 2004

  Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unit

  Topham, N., 2004, Patent No. US patent no. 6,754,806

  Research output: Patent

• Register File Circuitry

  Topham, N., 2004, Patent No. US patent no. 6,732,251

  Research output: Patent

• Renaming Registers to Values Produced by Instructions According to Assigned Produce Sequence Number

  Topham, N., 2004, Patent No. US patent no. 6,826,677

  Research output: Patent

• 2002

  Address translation

  Topham, N. & Lim, S., 3 Oct 2002, Patent No. US20020144078 A1, Priority date 30 Mar 2001

  Research output: Patent

  • Physical addresses 100%
  • Data storage equipment 97%
  • Virtual addresses 76%

• Handling of loops in processors

  Topham, N. & Livesley, R., 1 Oct 2002, Patent No. US 20020144092 A1

  Research output: Patent