Adaptive Hardware Systems with Novel Algorithmic Design & Guaranteed Resource Bounds

Project Details


The overall aims of this project are:
1. to provide dynamically reconfigurable hardware support for implementations of complex, dynamic signal processing algorithms;
2. to develop new software tools and notations capable of exploiting this dynamic hardware through formal analyses of time and power usage; and
3. to produce efficient parallel implementations of demanding signal processing applications.
The programme of work is split into three main work packages (WP1, WP2 and WP3).
The specific objectives of WP1 are:
* to extend Hume compilation, and time and space analyses, to hybrid architectures;
* to develop new models and analyses for Hume program power consumption;
* to enable dynamic reconfiguration of distributed systems on hybrid architectures driven by static time, space and power analyses of Hume components.
The specific objectives of WP2 are:
* to develop new processing architectures for the complex dynamic class of applications to be studied here
* to develop monitoring and task scheduling techniques for hardware devices which implement complex algorithms.
* to develop design techniques to realise the proposed monitoring and scheduling capabilities on the proposed architectures
The specific objectives of WP3 are:
* to develop efficient software and hardware implementations of RJMCMC methods for LiDAR by developing parallel forms of the algorithm and by using Hume to cost the time and space requirements of the algorithm;
* to design novel MIMO algorithms using sphere decoding and MCMC principles which can be easily implemented in hardware.

Layman's description

This project studied the development of new hardware and software design concepts to provide much more efficient platforms and signal processing techniques. The project studied LIDAR techniques for scanning targets at a distance using lasers and multiple antenna wireless systems as exemplars for the new design techniques.

Key findings

Digital processing of signals and images are frequently performed in many commercial electronic devices, including computer networks, mobile telephones and computer vision systems. However, at present there are no efficient design techniques that allow complex devices to be built up from a range of different computer processors. This means that current designs are often inefficient in terms of power usage and their responsiveness. Thus, a key requirement for the long-term exploitation of signal and image processing technologies lies in developing the increasingly complex processors that are required for high performance.
This project involved a rich inter-disciplinary collaboration between electronic engineers and computer scientists collectively aimed at overcoming fundamental challenges in high-performance computing applications. The work was structured in three major work packages. The first work package developed new implementations of algorithms developed using a new computer language called HUME onto field programmable gate array (FPGA) devices. The second work package developed new efficient processor designs for algorithm implementation on FPGAs and new detection algorithms for wireless communications. The third work package studied new serial and parallel implementation techniques for Lidar systems and new wireless algorithm designs for wireless communications.
More specificially, the research work at Edinburgh developed new efficient detection algorithms for multiple input-multiple output (MIMO) wireless systems, which use multiple antennas at both transmitter and receiver. These algorithms are more energy efficient than the state of the art fixed sphere decoder (FSD) algorithms. A new approach to soft-decoding in MIMO systems, called the parallel candidate scheme, was developed to reduce implementation delay compared to existing algorithms. Finally, the performance of transmitter precoding schemes for orthogonal frequency division multiplexing (OFDM) signals was studied and shown to provide a low complexity alternative to complex receiver processing algorithms such as the FSD approach.
AcronymISLAY Project
Effective start/end date1/07/0831/12/11


  • EPSRC: £351,040.00


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