Architecture and Compitler Infrastructure for Flexible Cellular Multiprocessing

We proposed a hybrid software-hardware mechanism for cache coherence in tiled CMPs with scalable on-chip interconnects. The mechanism relies on hardware to perform remote cache accesses and moves the responsibility for data mapping and coherence to the OS. We presented a tool that can be used to identify the breakdown of cache miss types and, thus, assist programmers in improving the data locality behavior of their programs. We proposed a novel class of hardware prefetchers that allow the global miss address stream to be first localized according to different correlation criteria and later chained following their original temporal behavior. This mechanism allows for the simultaneous exploitation of different types of correlation while maintaining timeliness. We proposed a new OS-managed policy for mapping memory blocks to caches in a tiled NUCA. This policy addresses the trade-off between cache access latency and number of off-chip accesses and also introduces an upper bound on the deviation of the distribution of memory pages among cache tiles. We presented a compiler scheme to automatically insert calls to run-time system functions to instrument code in order to generate performance models of parallel applications. The approach closes the gap between compiler-supported automatic model construction and the manual analytical modeling of workloads. We proposed a novel hybrid software-hardware coherence mechanism, where software is responsible for triggering the coherence actions - self-invalidations and writebacks - at appropriate times while hardware uses Bloom filters to perform more selective self-invalidations.