Error-tolerant Stream Processing System Design (ESP-SD)

  • Nagarajan, Vijay (Principal Investigator)
  • Grot, Boris (Co-investigator)

Project Details

StatusFinished
Effective start/end date30/11/1429/11/17

Funding

  • EPSRC: £441,324.00

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  • BTB-X: A Storage-Effective BTB Organization

    Asheim, T., Grot, B. & Kumar, R., 3 Sept 2021, In: IEEE Computer Architecture Letters. 20, 2, p. 134-137 4 p.

    Research output: Contribution to journalArticlepeer-review

  • DHTM: Durable Hardware Transactional Memory

    Joshi, A., Nagarajan, V., Cintra, M. & Viglas, S., 23 Jul 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). Los Angeles, California, USA: Institute of Electrical and Electronics Engineers, p. 452-465 14 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
    File
  • Blasting Through The Front-End Bottleneck With Shotgun

    Kumar, R., Grot, B. & Nagarajan, V., 19 Mar 2018, 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS ’18). Williamsburg, VA, USA: ACM, p. 30-42 13 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Open Access
    File