Optimisation of sub-100nm copper-interconnect and photoresist tracks for high density IC fabrication metrology

One of the most important elements of IC fabrication is the ability to produce structures with known and traceable dimensions. This project was a collaboration with NIST (National Institute of Standards and Technology – formerly the National Bureau of Standards) who are the leading international organisation developing traceable standards for the semiconductor industry. NIST have been in the forefront of undertaking the research to meet this requirement by developing the technology necessary to fabricate new standards which latterly has been based on the etch rate along different crystal planes. To take advantage of this (110) silicon has been used an approach that can produce vertical sidewalls that are atomically flat. Hence this technology can be used for linewidth standards.

Electrical measurements have long been seen as a good standard because of their repeatability and the relatively cheap measurement equipment. Electrical structures can be designed for measuring both linewidth and sheet resistance. With the sidewalls of the structure defining their linewidth, the conducting track width is invariant with depth. The key to the whole system is that the line is fabricated in single crystal silicon and if the number of atoms in the width of the structure is known then the linewidth can be determined to a known level of uncertainty related to the pitch of the atoms in the silicon. This can be determined using TEM technology and the atoms across the width of the track counted. This enable the electrical measurements to be directly compared to a reference standard.

This technology forms the basis for the project developments with the (110) silicon etching being used to form templates with vertical sidewall for other materials. The fact that (110) single crystal silicon is used then enables the linewidth to be determined.

One of the most important elements of microelectronic chip is the ability to produce structures with known and traceable dimensions. This project was a collaboration with NIST (National Institute of Standards and Technology – formerly the National Bureau of Standards) who are the leading international organisation developing traceable standards for the semiconductor industry. NIST have been in the forefront of undertaking the research to meet this requirement by developing the technology necessary to fabricate new linewidth standards to calibrate other linewidth measurement equipment. The key to this is being able to fabricate conducting bars with absolutely vertical sideways which can be achieved by designing structures that can be etched down the crystal planes of silicon wafers.
Electrical measurements have long been seen as a good standard because of their repeatability and the relatively cheap measurement equipment. In addition electrical structures can be designed for measuring both linewidth and sheet resistance. With the sidewalls of the structure defining their linewidth, this dimension is invariant with depth. The key to the whole system is that the line is fabricated in single crystal silicon and if the number of atoms in the width of the structure is known then the linewidth can be determined to a known level of uncertainty related to the known pitch of the atoms in the silicon. This can be determined using TEM technology and the atoms across the width of the track counted. This enable the electrical measurements of the same tracks to be directly compared to a reference standard.

This technology forms the basis for the project developments with the above vertical silicon etching being used to form templates with vertical sidewall for other materials. The fact that (110) single crystal silicon is used then enables the linewidth to be determined.

This one year project has achieved the following advances:
o Developed and demonstrated a process for the production of copper structures suitable for linewidth traceable standards.
o Demonstrated a process that can produce copper tracks (without conducting barriers) with vertical sidewalls and a width that can be directly determined from the number of silicon atoms in the silicon underlying the trench
o Implemented non-conducting barriers/adhesion layers for copper tracks which is essential if copper tracks are to be used for electrical line width extraction.
o Produced a methodology for the electrical extraction measurement of copper tracks width for structures fabricated using Single-Crystal Pre-form (SCP) technologies.