8.25μm Pitch 66% Fill Factor Global Shared Well SPAD Image Sensor in 40nm CMOS FSI Technology

Tarek Al abbas; Neale Dutton; Oscar Almer; Francesco Mattioli Della Rocca; Sara Pellegrini; Bruce R. Rae; D Golanski; Robert Henderson

8.25μm Pitch 66% Fill Factor Global Shared Well SPAD Image Sensor in 40nm CMOS FSI Technology

Tarek Al abbas
, Neale Dutton
, Oscar Almer
, Francesco Mattioli Della Rocca
, Sara Pellegrini
, Bruce R. Rae
, D Golanski
, Robert Henderson

School of Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

We present the first single photon avalanche
diode (SPAD) device and image sensor realized in a
customized 40nm CMOS front side illuminated (FSI)
technology. The 96×40 array utilizes a global shared well
layout structure with up to 66% fill factor at 8.25μm pitch
and median dark count rate (DCR) less than 70cps at 1V
excess bias. A rising edge to rising edge time gating
technique is demonstrated achieving a minimum time gate
of 360ps FWHM.

Original language	English
Number of pages	4
Publication status	Published - 2 Jun 2017
Event	International Image Sensor Workshop 2017 - Hiroshima, Japan Duration: 30 May 2017 → 2 Jun 2017

Workshop

Workshop	International Image Sensor Workshop 2017
Abbreviated title	IISW 2017
Country/Territory	Japan
City	Hiroshima
Period	30/05/17 → 2/06/17

Access to Document

AlAbbas_P10_IISW2017

Multiplexed 'Touch and Tell' Optical Molecular Sensing and Imaging
Henderson, R. (Principal Investigator)
EPSRC
1/10/13 → 31/03/19
Project: Research

Cite this

@conference{880e484a6adf4d908e169a927a1a1bde,

title = "8.25μm Pitch 66\% Fill Factor Global Shared Well SPAD Image Sensor in 40nm CMOS FSI Technology",

abstract = "We present the first single photon avalanche diode (SPAD) device and image sensor realized in a customized 40nm CMOS front side illuminated (FSI) technology. The 96×40 array utilizes a global shared well layout structure with up to 66\% fill factor at 8.25μm pitch and median dark count rate (DCR) less than 70cps at 1V excess bias. A rising edge to rising edge time gating technique is demonstrated achieving a minimum time gate of 360ps FWHM.",

author = "\{Al abbas\}, Tarek and Neale Dutton and Oscar Almer and \{Mattioli Della Rocca\}, Francesco and Sara Pellegrini and Rae, \{Bruce R.\} and D Golanski and Robert Henderson",

year = "2017",

month = jun,

day = "2",

language = "English",

note = "International Image Sensor Workshop 2017, IISW 2017 ; Conference date: 30-05-2017 Through 02-06-2017",

}

TY - CONF

T1 - 8.25μm Pitch 66% Fill Factor Global Shared Well SPAD Image Sensor in 40nm CMOS FSI Technology

AU - Al abbas, Tarek

AU - Dutton, Neale

AU - Almer, Oscar

AU - Mattioli Della Rocca, Francesco

AU - Pellegrini, Sara

AU - Rae, Bruce R.

AU - Golanski, D

AU - Henderson, Robert

PY - 2017/6/2

Y1 - 2017/6/2

N2 - We present the first single photon avalanche diode (SPAD) device and image sensor realized in a customized 40nm CMOS front side illuminated (FSI) technology. The 96×40 array utilizes a global shared well layout structure with up to 66% fill factor at 8.25μm pitch and median dark count rate (DCR) less than 70cps at 1V excess bias. A rising edge to rising edge time gating technique is demonstrated achieving a minimum time gate of 360ps FWHM.

AB - We present the first single photon avalanche diode (SPAD) device and image sensor realized in a customized 40nm CMOS front side illuminated (FSI) technology. The 96×40 array utilizes a global shared well layout structure with up to 66% fill factor at 8.25μm pitch and median dark count rate (DCR) less than 70cps at 1V excess bias. A rising edge to rising edge time gating technique is demonstrated achieving a minimum time gate of 360ps FWHM.

M3 - Paper

T2 - International Image Sensor Workshop 2017

Y2 - 30 May 2017 through 2 June 2017

ER -

8.25μm Pitch 66% Fill Factor Global Shared Well SPAD Image Sensor in 40nm CMOS FSI Technology

Abstract

Workshop

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Projects

Multiplexed 'Touch and Tell' Optical Molecular Sensing and Imaging

Cite this