A 3x3, 5µm pitch, 3-transistor Single Photon Avalanche Diode Array with Integrated 11V Bias Generation in 90nm CMOS Technology

Robert K. Henderson, Eric. A. G. Webster, Richard Walker, Justin A. Richardson, Lindsay A. Grant

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 3x3 prototype image sensor array consisting of 2µm diameter CMOS avalanche photodiodes with 3-transistor NMOS pixel circuitry is integrated in a 90nm CMOS image sensor technology. The 5µm pixel pitch is the smallest achieved to date and is obtained with < 1% crosstalk, 250Hz mean dark count rate (DCR) at 20C, 36% photon detection efficiency at 410nm (PDE) and 107ps FWHM jitter. The small pixel pitch makes it possible to recover the 12.5% fill factor by standard wafer-level microlenses. A 5-stage capacitive charge pump generates the 11V breakdown voltage from a standard 2.5V supply obviating external high voltage generation.

Original languageEnglish
Title of host publicationIEEE International Electron Devices Meeting (IEDM)
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages4
ISBN (Print)978-1-4244-7419-6
DOIs
Publication statusPublished - Dec 2010
EventIEEE International Electron Devices Meeting (IEDM) - San Francisco, United States
Duration: 6 Dec 20108 Dec 2010

Conference

ConferenceIEEE International Electron Devices Meeting (IEDM)
CountryUnited States
CitySan Francisco
Period6/12/108/12/10

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