A 77-dB DR 16-Ch 2nd-order $-$$ Neural Recording Chip with 0.0077mm2/Ch

Shiwei Wang, Marco Ballini, Xiaolin Yang, Chutham Sawigun, Jan-Willem Weijers, Dwaipayan Biswas, Carolina Mora Lopez

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

This paper presents a scalable 16-channel neural recording chip enabling simultaneous acquisition of action-potentials (APs), local-field potentials (LFPs), electrode DC offsets (EDOs) and stimulation artifacts (SAs) without saturation. By combining a DC-coupled Δ-ΔΣ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077mm 2 per channel, an input-referred noise of 5.53±0.36µV rms in the AP band and 2.88±0.18µV rms in the LFP band, a dynamic range (DR) of 77dB, an EDO tolerance of ±70mV and an input impedance of 283MΩ. The chip has been validated in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.
Original languageUndefined/Unknown
Title of host publication2021 Symposium on VLSI Circuits
PublisherIEEE
PagesC13-5
DOIs
Publication statusPublished - 28 Jul 2021
Event2021 Symposium on VLSI Circuits - Online
Duration: 13 Jun 202119 Jun 2021

Conference

Conference2021 Symposium on VLSI Circuits
Period13/06/2119/06/21

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