A comparison of data prefetching on an access decoupled and superscalar machine

G.P. Jones, N.P. Topham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We investigate the behavior of data prefetching on an access decoupled machine and a superscalar machine. We assess if there are benefits to using the decoupling paradigm given that an out-of-order (o-o-o) superscalar architecture could in principle prefetch to the same degree as an access decoupled machine. We have found that for large issue width the access decoupled machine can hide memory latency more effectively than a single instruction window o-o-o superscalar architecture. Our findings also demonstrate that an access decoupled machine offers the benefit of reducing the complexity of window issue logic.
Original languageEnglish
Title of host publicationMicroarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on
Pages65-70
Number of pages6
DOIs
Publication statusPublished - 1 Dec 1997

Keywords

  • cache storage
  • instruction sets
  • parallel architectures
  • parallel machines
  • performance evaluation
  • access decoupled machine
  • data prefetching
  • decoupling paradigm
  • large issue width
  • memory latency
  • out-of-order superscalar architecture
  • superscalar machine
  • window issue logic
  • Arithmetic
  • Clocks
  • Computer architecture
  • Computer science
  • Costs
  • Delay
  • Logic design
  • Microprocessors
  • Parallel processing
  • Prefetching

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