A compiler algorithm to reduce invalidation latency in virtual shared memory systems

Michael F. P. O'Boyle, Andy Nisbet, Rupert W. Ford

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a new compiler algorithm to eliminate invalidation traffic in virtual shared memory using a hybrid distributed invalidation scheme. It aggressively exploits static scheduling and data layout to accurately determine only those instances when invalidation is necessary, thus avoiding the additional read misses of previous schemes. Equations determining precisely what data should be invalidated are presented and followed by the derivation of approximations amenable to compiler manipulation. Compiler-directed invalidation in the presence of arbitrary control-flow is described and the definition of a compiler algorithm is presented. Preliminary experimental results on three programs show that this analysis can drastically reduce the amount of invalidation traffic and write misses
Original languageEnglish
Title of host publicationParallel Architectures and Compilation Techniques, 1996., Proceedings of the 1996 Conference on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages248-257
Number of pages10
ISBN (Print)0-8186-7633-7
DOIs
Publication statusPublished - 1996

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