TY - JOUR
T1 - A data-driven verilog-A ReRAM model
AU - Messaris, Ioannis
AU - Serb, Alexander
AU - Stathopoulos, Spyros
AU - Khiat, Ali
AU - Nikolaidis, Spyridon
AU - Prodromakis, Themistoklis
N1 - Funding Information:
Manuscript received June 4, 2017; revised September 14, 2017 and November 10, 2017; accepted December 20, 2017. Date of publication January 9, 2018; date of current version November 20, 2018. This work was supported in part by the EU COST Action (MEMOCIS) under Grant IC1401, and in part by the Engineering and Physical Sciences Research Council under Grant EP/K017829/1. This paper was recommended by Associate Editor Y. Wang. (Corresponding author: Ioannis Messaris.) I. Messaris and S. Nikolaidis are with the Department of Physics, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece (e-mail: [email protected]).
Publisher Copyright:
© 1982-2012 IEEE.
PY - 2018/12
Y1 - 2018/12
N2 - The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current-voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.
AB - The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current-voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.
KW - Characterization
KW - modeling
KW - resistive random access memory (ReRAM)
KW - simulation
KW - Verilog-A (VA)
UR - http://www.scopus.com/inward/record.url?scp=85041233054&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2018.2791468
DO - 10.1109/TCAD.2018.2791468
M3 - Article
AN - SCOPUS:85041233054
SN - 0278-0070
VL - 37
SP - 3151
EP - 3162
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 12
M1 - 8252766
ER -