A data-driven verilog-A ReRAM model

Ioannis Messaris*, Alexander Serb, Spyros Stathopoulos, Ali Khiat, Spyridon Nikolaidis, Themistoklis Prodromakis

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

The translation of emerging application concepts that exploit resistive random access memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model, where device current-voltage characteristics and resistive switching rate are expressed as a function of: 1) bias voltage and 2) initial resistive state (RS). The model versatility is validated on detailed characterization data, for both filamentary valence change memory and nonfilamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing RS response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools.

Original languageEnglish
Article number8252766
Pages (from-to)3151-3162
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number12
Early online date9 Jan 2018
Publication statusPublished - Dec 2018

Keywords / Materials (for Non-textual outputs)

  • Characterization
  • modeling
  • resistive random access memory (ReRAM)
  • simulation
  • Verilog-A (VA)


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