A fault-Tolerant ICAP controller with a selective-Area soft error mitigation engine

Adewale Adetomi, Godwin Enemali, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Dynamic partial reconfiguration (DPR) allows runtime access to the configuration memory (CMEM) of FPGAS. A key function that relies on DPR is task reconfiguration, where circuits are multiplexed in time and space in order to reduce device count and cost. Moreover, in mission-critical applications, DPR is used for soft error mitigation (SEM). These two key functions require access to the same CMEM interface and the recommendation is that more time (> 99%) should be allocated to SEM for continuous full-device reliability. We present a fault-Tolerant controller with a fully integrated SEM engine that allows selective-Area scanning of the FPGA in order to increase the time available for reconfiguration without compromising reliability. A case study drawn from the NASA JPL's Compositional InfraRed Imaging Spectrometer (CIRIS) instrument shows a time saving of up to 74% over the Xilinx SEM IP when only the data processing core of the CIRIS instrument is considered.

Original languageEnglish
Title of host publication2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages192-199
Number of pages8
ISBN (Electronic)9781538634394
DOIs
Publication statusPublished - 19 Sep 2017
Event2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017 - Pasadena, United States
Duration: 24 Jul 201727 Jul 2017

Publication series

Name2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017

Conference

Conference2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017
Country/TerritoryUnited States
CityPasadena
Period24/07/1727/07/17

Keywords

  • FPGA
  • ICAP controller
  • partial reconfiguration
  • soft error mitigation

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