A (Fault-Tolerant)(2) Scheduler for Real-Time HW Tasks

Xabier Iturbe*, Khaled Benkrid, Tughrul Arslan, Mikel Azkarate, Imanol Martinez

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

This paper describes a fault-tolerant scheduler that uses the Area-Time response Balancing algorithm (ATB) for scheduling real-time hardware tasks onto partially recontigurable FPGAs. The architecture of the ATB scheduler incorporates fault-tolerance by design features; including Triple Modular Redundancy (TMR), parity protection of its memories and finite state machines, as well as spatial and implementation diversity. Additionally, it is able to scrub soft-errors and circumvent the permanent damage in the device. Besides the scheduling circuit is itself fault-tolerant, ATB is aware of the occurring faults in the silicon substrate of the chip, leading to a very reliable "fault-tolerant square scheduling".

Original languageEnglish
Title of host publicationRECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS
EditorsA Koch, R Krishnamurthy, J McAllister, R Woods, T ElGhazawi
Place of PublicationBERLIN
PublisherSpringer
Pages79-87
Number of pages9
ISBN (Print)978-3-642-19474-0
Publication statusPublished - 2011
Event7th International Symposium on Applied Reconfigurable Computing, ARC 2011 - Belfast, United Kingdom
Duration: 23 Mar 201125 Mar 2011

Publication series

NameLecture Notes in Computer Science
PublisherSPRINGER-VERLAG BERLIN
Volume6578
ISSN (Print)0302-9743

Conference

Conference7th International Symposium on Applied Reconfigurable Computing, ARC 2011
Country/TerritoryUnited Kingdom
Period23/03/1125/03/11

Keywords / Materials (for Non-textual outputs)

  • Real-Time Scheduling
  • Fault-Tolerance
  • Reconfigurable Computing
  • Hardware Virtualization

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