A fully asynchronous superscalar architecture

D. K. Arvind, R. D. Mullins

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An asynchronous superscalar architecture is presented based on a novel architectural feature called instruction compounding. This enables efficient dynamic scheduling and forwarding of data based on local information, while maintaining the advantages of asynchrony in terms of exploiting actual delays. Results are presented in which statically and dynamically compounded architectures are compared against an equivalent synchronous superscalar architecture
Original languageEnglish
Title of host publicationParallel Architectures and Compilation Techniques, 1999. Proceedings. 1999 International Conference on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages17-22
Number of pages6
ISBN (Print)0-7695-0425-6
DOIs
Publication statusPublished - 1999

Keywords

  • parallel architectures
  • processor scheduling
  • data forwarding
  • delays
  • dynamically compounded architectures
  • efficient dynamic scheduling
  • fully asynchronous superscalar architecture
  • instruction compounding
  • local information
  • statically compounded architectures
  • Asynchronous circuits
  • Clocks
  • Electromagnetic interference
  • Frequency
  • Informatics
  • Logic
  • Pipelines
  • Power dissipation
  • Signal design
  • Signal processing

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