A Gate Modulated Avalanche Bipolar Transistor in 130nm CMOS Technology

Robert Henderson; E.A.G. Webster; Richard Walker

doi:10.1109/ESSDERC.2012.6343374

A Gate Modulated Avalanche Bipolar Transistor in 130nm CMOS Technology

Robert Henderson, E.A.G. Webster, Richard Walker

School of Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract / Description of output

A novel Geiger-mode avalanche bipolar transistor
structure is realized in a 130nm, low-voltage CMOS technology.
A MOS transistor formed within the base region of the device
allows gate modulation of the output pulse rate. In bipolar
operation, the device generates Poisson-distributed digital
output pulses at rates from 1kHz to 20MHz, linearly related to
emitter currents in the range 10nA to 1μA. In MOS operation,
the mean pulse rate varies exponentially over 4-5 decades as the
gate voltage changes by 300mV and consumes less than 180μA
drain-source current. The gate input eliminates the input
current of the avalanche bipolar transistor, enabling capacitive
sensor interfaces and direct device-level, analogue-digital
conversion. The device is fully compatible with low-voltage
CMOS circuits and standard digital process steps.

Original language	English
Pages	226-229
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDERC.2012.6343374
Publication status	Published - Sept 2012
Event	European Solid-State Device Research Conference - Bordeaux, France Duration: 17 Sept 2012 → 21 Sept 2012

Conference

Conference	European Solid-State Device Research Conference
Country/Territory	France
City	Bordeaux
Period	17/09/12 → 21/09/12

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10.1109/ESSDERC.2012.6343374

http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6343374

Cite this

@conference{e1e788df434b4efe9ea92696d257aad4,

title = "A Gate Modulated Avalanche Bipolar Transistor in 130nm CMOS Technology",

abstract = "A novel Geiger-mode avalanche bipolar transistor structure is realized in a 130nm, low-voltage CMOS technology. A MOS transistor formed within the base region of the device allows gate modulation of the output pulse rate. In bipolar operation, the device generates Poisson-distributed digital output pulses at rates from 1kHz to 20MHz, linearly related to emitter currents in the range 10nA to 1μA. In MOS operation, the mean pulse rate varies exponentially over 4-5 decades as the gate voltage changes by 300mV and consumes less than 180μA drain-source current. The gate input eliminates the input current of the avalanche bipolar transistor, enabling capacitive sensor interfaces and direct device-level, analogue-digital conversion. The device is fully compatible with low-voltage CMOS circuits and standard digital process steps.",

author = "Robert Henderson and E.A.G. Webster and Richard Walker",

year = "2012",

month = sep,

doi = "10.1109/ESSDERC.2012.6343374",

language = "English",

pages = "226--229",

note = "European Solid-State Device Research Conference ; Conference date: 17-09-2012 Through 21-09-2012",

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TY - CONF

T1 - A Gate Modulated Avalanche Bipolar Transistor in 130nm CMOS Technology

AU - Henderson, Robert

AU - Webster, E.A.G.

AU - Walker, Richard

PY - 2012/9

Y1 - 2012/9

N2 - A novel Geiger-mode avalanche bipolar transistor structure is realized in a 130nm, low-voltage CMOS technology. A MOS transistor formed within the base region of the device allows gate modulation of the output pulse rate. In bipolar operation, the device generates Poisson-distributed digital output pulses at rates from 1kHz to 20MHz, linearly related to emitter currents in the range 10nA to 1μA. In MOS operation, the mean pulse rate varies exponentially over 4-5 decades as the gate voltage changes by 300mV and consumes less than 180μA drain-source current. The gate input eliminates the input current of the avalanche bipolar transistor, enabling capacitive sensor interfaces and direct device-level, analogue-digital conversion. The device is fully compatible with low-voltage CMOS circuits and standard digital process steps.

AB - A novel Geiger-mode avalanche bipolar transistor structure is realized in a 130nm, low-voltage CMOS technology. A MOS transistor formed within the base region of the device allows gate modulation of the output pulse rate. In bipolar operation, the device generates Poisson-distributed digital output pulses at rates from 1kHz to 20MHz, linearly related to emitter currents in the range 10nA to 1μA. In MOS operation, the mean pulse rate varies exponentially over 4-5 decades as the gate voltage changes by 300mV and consumes less than 180μA drain-source current. The gate input eliminates the input current of the avalanche bipolar transistor, enabling capacitive sensor interfaces and direct device-level, analogue-digital conversion. The device is fully compatible with low-voltage CMOS circuits and standard digital process steps.

U2 - 10.1109/ESSDERC.2012.6343374

DO - 10.1109/ESSDERC.2012.6343374

M3 - Paper

SP - 226

EP - 229

T2 - European Solid-State Device Research Conference

Y2 - 17 September 2012 through 21 September 2012

ER -

A Gate Modulated Avalanche Bipolar Transistor in 130nm CMOS Technology

Abstract / Description of output

Conference

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