A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

Zhenyu Liu; Tughrul Arslan; Sami Khawam; Iain Lindsay

A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, powerful function and low power consumption. A reconfigurable Finite State Machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC. This paper presents a novel unbalanced unsymmetrical reconfigurable architecture for generic FSM; Compared with commercial FPGA devices, the new architecture results in area reduction of 43% and power consumption decrease of 82%.

Original language	English
Title of host publication	ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2
Place of Publication	NEW YORK
Publisher	Institute of Electrical and Electronics Engineers
Pages	639-644
Number of pages	6
ISBN (Print)	0-7803-8736-8
Publication status	Published - 2005
Event	10th Asia and South Pacific Design Automation Conference - Shanghai Duration: 18 Jan 2005 → 21 Jan 2005

Conference

Conference	10th Asia and South Pacific Design Automation Conference
City	Shanghai
Period	18/01/05 → 21/01/05

Cite this

@inproceedings{14275b1e0ea14a66a1a16224c48cb0b3,

title = "A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines",

abstract = "The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, powerful function and low power consumption. A reconfigurable Finite State Machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC. This paper presents a novel unbalanced unsymmetrical reconfigurable architecture for generic FSM; Compared with commercial FPGA devices, the new architecture results in area reduction of 43% and power consumption decrease of 82%.",

author = "Zhenyu Liu and Tughrul Arslan and Sami Khawam and Iain Lindsay",

year = "2005",

language = "English",

isbn = "0-7803-8736-8",

pages = "639--644",

booktitle = "ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "10th Asia and South Pacific Design Automation Conference ; Conference date: 18-01-2005 Through 21-01-2005",

}

Liu, Z, Arslan, T, Khawam, S & Lindsay, I 2005, A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines. in ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2. Institute of Electrical and Electronics Engineers, NEW YORK, pp. 639-644, 10th Asia and South Pacific Design Automation Conference, Shanghai, 18/01/05.

A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines. / Liu, Zhenyu; Arslan, Tughrul; Khawam, Sami et al.
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2. NEW YORK: Institute of Electrical and Electronics Engineers, 2005. p. 639-644.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

AU - Liu, Zhenyu

AU - Arslan, Tughrul

AU - Khawam, Sami

AU - Lindsay, Iain

PY - 2005

Y1 - 2005

N2 - The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, powerful function and low power consumption. A reconfigurable Finite State Machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC. This paper presents a novel unbalanced unsymmetrical reconfigurable architecture for generic FSM; Compared with commercial FPGA devices, the new architecture results in area reduction of 43% and power consumption decrease of 82%.

AB - The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, powerful function and low power consumption. A reconfigurable Finite State Machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC. This paper presents a novel unbalanced unsymmetrical reconfigurable architecture for generic FSM; Compared with commercial FPGA devices, the new architecture results in area reduction of 43% and power consumption decrease of 82%.

M3 - Conference contribution

SN - 0-7803-8736-8

SP - 639

EP - 644

BT - ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2

PB - Institute of Electrical and Electronics Engineers

CY - NEW YORK

T2 - 10th Asia and South Pacific Design Automation Conference

Y2 - 18 January 2005 through 21 January 2005

ER -

A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

Abstract

Conference

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