A machine learning-based approach for thread mapping on transactional memory applications

M. Castro, L.F.W. Goes, C.P. Ribeiro, M. Cole, M. Cintra, J.-F. Mehaut

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Thread mapping has been extensively used as a technique to efficiently exploit memory hierarchy on modern chip-multiprocessors. It places threads on cores in order to amortize memory latency and/or to reduce memory contention. However, efficient thread mapping relies upon matching application behavior with system characteristics. Particularly, Software Transactional Memory (STM) applications introduce another dimension due to its runtime system support. Existing STM systems implement several conflict detection and resolution mechanisms, which leads STM applications to behave differently for each combination of these mechanisms. In this paper we propose a machine learning-based approach to automatically infer a suitable thread mapping strategy for transactional memory applications. First, we profile several STM applications from the STAMP benchmark suite considering application, STM system and platform features to build a set of input instances. Then, such data feeds a machine learning algorithm, which produces a decision tree able to predict the most suitable thread mapping strategy for new unobserved instances. Results show that our approach improves performance up to 18.46% compared to the worst case and up to 6.37% over the Linux default thread mapping strategy.
Original languageEnglish
Title of host publicationHigh Performance Computing (HiPC), 2011 18th International Conference on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages1 -10
Number of pages10
ISBN (Electronic)978-1-4577-1949-3
ISBN (Print)978-1-4577-1951-6
Publication statusPublished - 1 Dec 2011


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