A memristor-CMOS hybrid architecture concept for on-line template matching

The ability to identify (detect) and categorise (sort) neural spikes in real-time and under highly restrictive power/area budgets is a major enabling technology towards the development of intelligent implantable systems. In this work we propose a memristor-CMOS hybrid architecture concept that relies on a 'template pixel' (texel) circuit combining CMOS and memristive devices to perform on-line spike sorting through template matching. We show through simulation how the texel is capable of comparing an input voltage against a stored (in the memristors) value and converting the degree of matching between input and stored pattern into a current. We further illustrate the fundamental texel design space that includes tuning it to a different preferred input voltage and controlling the sharpness of the tuning. Finally, we estimate that even in an unoptimised technology and design a texel array capable of recognising three different 10-point patterns will consume a very promising maximum of 3.15 μW for a footprint of approx. 500 μτω2.