A mini-SiPM array for PET detectors implemented in 0.35-μm HV CMOS technology

Leo H.C. Braga*, Lucio Pancheri, Leonardo Gasparini, Robert K. Henderson, David Stoppa

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

A new architecture for Positron Emission Tomography visible-light detectors is presented. The architecture is based on mini-SiPMs (arrays of 32 SPADs), which are locally digitized. With this architecture we expect to achieve a high fill factor while still performing an early enough analog-to-digital conversion so as to avoid interconnect parasitics common of standard SiPMs. The detector is implemented as a 14 × 10 pixel array where each pixel contains a mini-SiPM, a digital counter and individual SPAD SRAMs for disabling high DCR devices. The achieved fill factor is 29% and the expected maximum event rate is 16 kcps.

Original languageEnglish
Title of host publication2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2011 - Conference Proceedings
Pages181-184
Number of pages4
DOIs
Publication statusPublished - 5 Sept 2011
Event2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2011 - Madonna di Campiglio, Trento, Italy
Duration: 3 Jul 20117 Jul 2011

Publication series

Name2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2011 - Conference Proceedings

Conference

Conference2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2011
Country/TerritoryItaly
CityMadonna di Campiglio, Trento
Period3/07/117/07/11

Keywords / Materials (for Non-textual outputs)

  • digital SiPM
  • HV CMOS
  • mini-SiPM
  • PET
  • SiPM
  • SPAD

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