A novel approach for reducing the area occupied by contact pads on process control chips

A J WALTON, W GAMMIE, D MORROW, J T M STEVENSON, R J HOLWILL, Anthony Walton

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.
Original languageEnglish
Title of host publicationProceedings 1990 IEEE International Conference on Microelectronic Test Structures
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages75-80
Number of pages6
DOIs
Publication statusPublished - Mar 1990
Event1990 INTERNATIONAL CONF ON MICROELECTRONIC TEST STRUCTURES ( ICMTS 90 ) - SAN DIEGO
Duration: 5 Mar 19907 Mar 1990

Conference

Conference1990 INTERNATIONAL CONF ON MICROELECTRONIC TEST STRUCTURES ( ICMTS 90 )
CitySAN DIEGO
Period5/03/907/03/90

Keywords

  • Ammeters
  • Atherosclerosis
  • Contacts
  • Electric variables measurement
  • Electrical resistance measurement
  • Force measurement
  • Integrated circuit interconnections
  • Process control
  • Resistors
  • Testing

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