A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology

M. Gersbach, Y. Maruyama, E. Labonne, R. Walker, Robert Henderson, F. Borghetti, D. Stoppa, E. Charbon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mum in both directions and with a total TDC area of less than 2000 mum2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).
Original languageEnglish
Title of host publicationIEEE European Solid-State Circuits Conference (ESSCIRC)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages196 - 199
ISBN (Print)978-1-4244-4354-3
DOIs
Publication statusPublished - 14 Sep 2009
EventIEEE European Solid-State Circuits Conference (ESSCIRC) - Athens, Greece
Duration: 14 Sep 200918 Sep 2009

Conference

ConferenceIEEE European Solid-State Circuits Conference (ESSCIRC)
CountryGreece
CityAthens
Period14/09/0918/09/09

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