A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology

M. Gersbach; Y. Maruyama; E. Labonne; R. Walker; Robert Henderson; F. Borghetti; D. Stoppa; E. Charbon

doi:10.1109/ESSCIRC.2009.5326021

A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology

M. Gersbach, Y. Maruyama, E. Labonne, R. Walker, Robert Henderson, F. Borghetti, D. Stoppa, E. Charbon

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mum in both directions and with a total TDC area of less than 2000 mum2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).

Original language	English
Title of host publication	IEEE European Solid-State Circuits Conference (ESSCIRC)
Publisher	Institute of Electrical and Electronics Engineers
Pages	196 - 199
ISBN (Print)	978-1-4244-4354-3
DOIs	https://doi.org/10.1109/ESSCIRC.2009.5326021
Publication status	Published - 14 Sept 2009
Event	IEEE European Solid-State Circuits Conference (ESSCIRC) - Athens, Greece Duration: 14 Sept 2009 → 18 Sept 2009

Conference

Conference	IEEE European Solid-State Circuits Conference (ESSCIRC)
Country/Territory	Greece
City	Athens
Period	14/09/09 → 18/09/09

Access to Document

10.1109/ESSCIRC.2009.5326021

Cite this

Gersbach, M., Maruyama, Y., Labonne, E., Walker, R., Henderson, R., Borghetti, F., Stoppa, D., & Charbon, E. (2009). A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology. In IEEE European Solid-State Circuits Conference (ESSCIRC) (pp. 196 - 199). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSCIRC.2009.5326021

@inproceedings{45f6ff762617442d856c0c8bb325cd6b,

title = "A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology",

abstract = "We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mum in both directions and with a total TDC area of less than 2000 mum2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).",

author = "M. Gersbach and Y. Maruyama and E. Labonne and R. Walker and Robert Henderson and F. Borghetti and D. Stoppa and E. Charbon",

year = "2009",

month = sep,

day = "14",

doi = "10.1109/ESSCIRC.2009.5326021",

language = "English",

isbn = "978-1-4244-4354-3",

pages = "196 -- 199",

booktitle = "IEEE European Solid-State Circuits Conference (ESSCIRC)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "IEEE European Solid-State Circuits Conference (ESSCIRC) ; Conference date: 14-09-2009 Through 18-09-2009",

}

Gersbach, M, Maruyama, Y, Labonne, E, Walker, R, Henderson, R, Borghetti, F, Stoppa, D & Charbon, E 2009, A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology. in IEEE European Solid-State Circuits Conference (ESSCIRC). Institute of Electrical and Electronics Engineers, pp. 196 - 199, IEEE European Solid-State Circuits Conference (ESSCIRC), Athens, Greece, 14/09/09. https://doi.org/10.1109/ESSCIRC.2009.5326021

TY - GEN

T1 - A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology

AU - Gersbach, M.

AU - Maruyama, Y.

AU - Labonne, E.

AU - Walker, R.

AU - Henderson, Robert

AU - Borghetti, F.

AU - Stoppa, D.

AU - Charbon, E.

PY - 2009/9/14

Y1 - 2009/9/14

N2 - We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mum in both directions and with a total TDC area of less than 2000 mum2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).

AB - We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mum in both directions and with a total TDC area of less than 2000 mum2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).

UR - http://www.scopus.com/inward/record.url?scp=72849153263&partnerID=8YFLogxK

U2 - 10.1109/ESSCIRC.2009.5326021

DO - 10.1109/ESSCIRC.2009.5326021

M3 - Conference contribution

SN - 978-1-4244-4354-3

SP - 196

EP - 199

BT - IEEE European Solid-State Circuits Conference (ESSCIRC)

PB - Institute of Electrical and Electronics Engineers

T2 - IEEE European Solid-State Circuits Conference (ESSCIRC)

Y2 - 14 September 2009 through 18 September 2009

ER -

A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology

Abstract

Conference

Access to Document

Other files and links

Fingerprint

MEGAFRAME: MEGAFRAME: Million Frame Per Second, Time Correlated Single Photon Camera

Cite this

A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Projects

MEGAFRAME: MEGAFRAME: Million Frame Per Second, Time Correlated Single Photon Camera

Cite this