Projects per year
Abstract
We report on the design and characterization of a 32 times 32 time-to-digital converter (TDC) array implemented in a 130 nm imaging CMOS technology. The 10-bit TDCs exhibit a timing resolution of 119 ps with a timing uniformity across the entire array of less than 2 LSBs. The differential- and integral non-linearity (DNL and INL) were measured at plusmn 0.4 and plusmn1.2 LSBs respectively. The TDC array was fabricated with a pitch of 50 mum in both directions and with a total TDC area of less than 2000 mum2. The characteristics of the array make it an excellent candidate for in-pixel TDC in time-resolved imagers for applications such as 3-D imaging and fluorescence lifetime imaging microscopy (FLIM).
Original language | English |
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Title of host publication | IEEE European Solid-State Circuits Conference (ESSCIRC) |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 196 - 199 |
ISBN (Print) | 978-1-4244-4354-3 |
DOIs | |
Publication status | Published - 14 Sept 2009 |
Event | IEEE European Solid-State Circuits Conference (ESSCIRC) - Athens, Greece Duration: 14 Sept 2009 → 18 Sept 2009 |
Conference
Conference | IEEE European Solid-State Circuits Conference (ESSCIRC) |
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Country/Territory | Greece |
City | Athens |
Period | 14/09/09 → 18/09/09 |
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Dive into the research topics of 'A Parallel 32x32 Time-To-Digital Converter Array Fabricated in a 130 nm Imaging CMOS Technology'. Together they form a unique fingerprint.Projects
- 1 Finished
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MEGAFRAME: MEGAFRAME: Million Frame Per Second, Time Correlated Single Photon Camera
Henderson, R. (Principal Investigator) & Crain, J. (Co-investigator)
1/06/06 → 30/04/10
Project: Research