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Abstract
In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core x86 host machine for as many as 2,048 target processors whilst exhibiting minimal and near constant overhead, including memory considerations.
Original language | English |
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Pages (from-to) | 212-235 |
Number of pages | 24 |
Journal | International journal of parallel programming |
Volume | 41 |
Issue number | 2 |
DOIs | |
Publication status | Published - Apr 2013 |
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Dive into the research topics of 'A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation'. Together they form a unique fingerprint.Projects
- 1 Finished
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Dynamic Adaptation in Hetrogeneous Multicore Embedded Processors
Haas, H., Franke, B., O'Boyle, M. & Topham, N.
1/11/10 → 30/07/14
Project: Research