A Partial Scan Based Test Generation for Asynchronous Circuits

D.P. Vasudevan, Aristides Efthymiou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Test Generation for asynchronous circuit is a hard problem mainly due to the absence of a global clock. Full scan design based test generation of asynchronous circuits seems to be feasible but at an expense of large area overhead. Partial scan should be a better option with lower area overhead but there is no known systematic way of selecting which asynchronous state-holding elements to scan. This paper presents a partial scan and automatic test generation methodology based on a novel adaptation of BALLAST for asynchronous circuits and time frame unrolling. Balanced structures are used to guide the selection of the state-holding elements that will be scanned. A cyclic to acyclic conversion of the input circuit is used to create a combinational circuit for which test patterns are easily generated using well known methods. These test patterns are then used to test the original circuit. Fault coverage and area overhead results of this method are obtained and analyzed with full scan and other methods.
Original languageEnglish
Title of host publicationDesign and Diagnostics of Electronic Circuits and Systems, 2008. DDECS 2008. 11th IEEE Workshop on
Number of pages4
ISBN (Electronic)978-1-4244-2277-7
Publication statusPublished - 1 Apr 2008

Keywords / Materials (for Non-textual outputs)

  • Balanced structures
  • acyclic conversion
  • asynchronous circuits
  • asynchronous state-holding elements
  • automatic test generation methodology
  • combinational circuit
  • cyclic conversion
  • full scan design
  • global clock
  • partial scan based test generation
  • automatic test pattern generation
  • network synthesis


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