A placement management circuit for efficient realtime hardware reuse on FPGAs targeting reliable autonomous systems

Godwin Enemali, Adewale Adetomi, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Reconfigurable hardware such as FPGAs offer promising platform for the development of embedded autonomous systems. This is due to their unique combination of high performance and flexibility. However, state-of-the-art FPGAs have large reconfiguration time, which often leads to missed deadlines in real-time systems. They also suffer from considerable fragmentation during runtime placement, leading to poor chip area utilization. In this paper, we present a novel hardware-placement management circuit to address these limitations by offering circuit reuse and a low-cost defragmentation. Its implementation occupies only 1852 FPGA slices. Our results showed that over 70% of configuration time was circumvented compared to state-of-the-art techniques. In addition, up to 56% improvement in reuse efficiency was observed.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
Publication statusPublished - 25 Sep 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: 28 May 201731 May 2017

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/TerritoryUnited States
CityBaltimore
Period28/05/1731/05/17

Keywords

  • defragmentation
  • FPGA task reuse
  • hardware scheduling
  • placement
  • Reconfigurable hardware
  • reconfiguration overhead

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