A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design

S. Danesh, J. E. D. Hurwitz, K. M. Findlater, Robert Henderson, David Renshaw

Research output: Contribution to journalArticlepeer-review

Abstract

A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-independent current consumption. A 128-channel counter ADC, implemented in 0.13 μm CMOS, can be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope ramp-generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nanometer CMOS technologies.
Original languageEnglish
Pages (from-to)733 - 748
JournalIEEE Journal of Solid-State Circuits
Volume48
Issue number3
DOIs
Publication statusPublished - Mar 2013

Keywords

  • Bottom plate ramping
  • TIC ADC
  • Time Interleaved Counter ADC
  • comparator based ADC
  • global ramp generator
  • single slope

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