A Reconfigurable 1GSps to 250MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC in 0.13μm CMOS

Research output: Contribution to conference › Paper › peer-review

Original language	English
Pages	268-269
Number of pages	2
Publication status	Published - 15 Jun 2011
Event	2011 Symposium on VLSI Circuits - , Japan Duration: 15 Jun 2011 → 17 Jun 2011

Cite this

@conference{a616f289b2094e0f9538a434133f4717,

title = "A Reconfigurable 1GSps to 250MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC in 0.13μm CMOS",

author = "S. Danesh and Hurwitz, \{J. E. D.\} and Findlater, \{K. M.\} and David Renshaw and Robert Henderson",

year = "2011",

month = jun,

day = "15",

language = "English",

pages = "268--269",

note = "2011 Symposium on VLSI Circuits ; Conference date: 15-06-2011 Through 17-06-2011",

}