A Reconfigurable 40 nm CMOS SPAD Array for LiDAR Receiver Validation

Sarrah Patanwala, Istvan Gyongy, Neale Dutton, Bruce R. Rae, Robert Henderson

Research output: Contribution to conferencePosterpeer-review

Abstract / Description of output

We present a reconfigurable single photon
avalanche diode (SPAD) array realised in 40 nm CMOS
technology interfaced to a Xilinx Kintex-7 FPGA,
providing the capability to readout 128 channels at
100MHz simultaneously. A Synchronous Summation
Technique (SST) to maximise photon detection rate in
applications such as automotive LiDAR is proposed
demonstrating a 7.5× increase in dynamic range of the
system over current state-of the art. A simulation model to
optimise LiDAR receiver design considering a wide range
of parameters is described. Measurements with the test
array and a TDC implemented on FPGA are provided to
validate the simulations.
Original languageEnglish
Number of pages4
Publication statusPublished - 23 Jun 2019
EventInternational Image Sensor Workshop - Snowbird Resort, Snowbird, United States
Duration: 23 Jun 201927 Dec 2019


WorkshopInternational Image Sensor Workshop
Abbreviated titleIISW
Country/TerritoryUnited States
Internet address


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