A Reconfigurable 40 nm CMOS SPAD Array for LiDAR Receiver Validation

Sarrah Patanwala; Istvan Gyongy; Neale Dutton; Bruce R. Rae; Robert Henderson

A Reconfigurable 40 nm CMOS SPAD Array for LiDAR Receiver Validation

Sarrah Patanwala, Istvan Gyongy, Neale Dutton, Bruce R. Rae, Robert Henderson

School of Engineering

Research output: Contribution to conference › Poster › peer-review

Abstract

We present a reconfigurable single photon
avalanche diode (SPAD) array realised in 40 nm CMOS
technology interfaced to a Xilinx Kintex-7 FPGA,
providing the capability to readout 128 channels at
100MHz simultaneously. A Synchronous Summation
Technique (SST) to maximise photon detection rate in
applications such as automotive LiDAR is proposed
demonstrating a 7.5× increase in dynamic range of the
system over current state-of the art. A simulation model to
optimise LiDAR receiver design considering a wide range
of parameters is described. Measurements with the test
array and a TDC implemented on FPGA are provided to
validate the simulations.

Original language	English
Number of pages	4
Publication status	Published - 23 Jun 2019
Event	International Image Sensor Workshop - Snowbird Resort, Snowbird, United States Duration: 23 Jun 2019 → 27 Dec 2019 https://imagesensors.org/2019-international-image-sensor-workshop/

Workshop

Workshop	International Image Sensor Workshop
Abbreviated title	IISW
Country/Territory	United States
City	Snowbird
Period	23/06/19 → 27/12/19
Internet address	https://imagesensors.org/2019-international-image-sensor-workshop/

Access to Document

https://www.imagesensors.org/Past%20Workshops/2019%20Workshop/2019%20Papers/P02.pdf

PhD Student Support- as part of the UoE/STMicroelectronic Research Collaboration
Henderson, R.
UK industry, commerce and public corporations
1/01/11 → 29/02/20
Project: Research

Cite this

@conference{59e26f677cbc4166b3d5b06e1d040d4a,

title = "A Reconfigurable 40 nm CMOS SPAD Array for LiDAR Receiver Validation",

abstract = "We present a reconfigurable single photonavalanche diode (SPAD) array realised in 40 nm CMOStechnology interfaced to a Xilinx Kintex-7 FPGA,providing the capability to readout 128 channels at100MHz simultaneously. A Synchronous SummationTechnique (SST) to maximise photon detection rate inapplications such as automotive LiDAR is proposeddemonstrating a 7.5× increase in dynamic range of thesystem over current state-of the art. A simulation model tooptimise LiDAR receiver design considering a wide rangeof parameters is described. Measurements with the testarray and a TDC implemented on FPGA are provided tovalidate the simulations. ",

author = "Sarrah Patanwala and Istvan Gyongy and Neale Dutton and Rae, {Bruce R.} and Robert Henderson",

year = "2019",

month = jun,

day = "23",

language = "English",

note = "International Image Sensor Workshop, IISW ; Conference date: 23-06-2019 Through 27-12-2019",

url = "https://imagesensors.org/2019-international-image-sensor-workshop/",

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TY - CONF

T1 - A Reconfigurable 40 nm CMOS SPAD Array for LiDAR Receiver Validation

AU - Patanwala, Sarrah

AU - Gyongy, Istvan

AU - Dutton, Neale

AU - Rae, Bruce R.

AU - Henderson, Robert

PY - 2019/6/23

Y1 - 2019/6/23

N2 - We present a reconfigurable single photonavalanche diode (SPAD) array realised in 40 nm CMOStechnology interfaced to a Xilinx Kintex-7 FPGA,providing the capability to readout 128 channels at100MHz simultaneously. A Synchronous SummationTechnique (SST) to maximise photon detection rate inapplications such as automotive LiDAR is proposeddemonstrating a 7.5× increase in dynamic range of thesystem over current state-of the art. A simulation model tooptimise LiDAR receiver design considering a wide rangeof parameters is described. Measurements with the testarray and a TDC implemented on FPGA are provided tovalidate the simulations.

AB - We present a reconfigurable single photonavalanche diode (SPAD) array realised in 40 nm CMOStechnology interfaced to a Xilinx Kintex-7 FPGA,providing the capability to readout 128 channels at100MHz simultaneously. A Synchronous SummationTechnique (SST) to maximise photon detection rate inapplications such as automotive LiDAR is proposeddemonstrating a 7.5× increase in dynamic range of thesystem over current state-of the art. A simulation model tooptimise LiDAR receiver design considering a wide rangeof parameters is described. Measurements with the testarray and a TDC implemented on FPGA are provided tovalidate the simulations.

M3 - Poster

T2 - International Image Sensor Workshop

Y2 - 23 June 2019 through 27 December 2019

ER -

A Reconfigurable 40 nm CMOS SPAD Array for LiDAR Receiver Validation

Abstract

Workshop

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Projects

PhD Student Support- as part of the UoE/STMicroelectronic Research Collaboration

Cite this