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On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.
|Title of host publication||Proceedings of the 8th ACM International Conference on Computing Frontiers|
|Place of Publication||New York, NY, USA|
|Number of pages||2|
|Publication status||Published - 2011|
- cache tuning, configurable cache, smart cache