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Abstract
On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.
Original language | English |
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Title of host publication | Proceedings of the 8th ACM International Conference on Computing Frontiers |
Place of Publication | New York, NY, USA |
Publisher | ACM |
Pages | 9:1-9:2 |
Number of pages | 2 |
DOIs | |
Publication status | Published - 2011 |
Publication series
Name | CF '11 |
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Publisher | ACM |
Keywords / Materials (for Non-textual outputs)
- cache tuning, configurable cache, smart cache
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Dive into the research topics of 'A Reconfigurable Cache Architecture for Energy Efficiency'. Together they form a unique fingerprint.Projects
- 1 Finished
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Dynamic Adaptation in Hetrogeneous Multicore Embedded Processors
Haas, H., Franke, B., O'Boyle, M. & Topham, N.
1/11/10 → 30/07/14
Project: Research