A Reconfigurable Cache Architecture for Energy Efficiency

Karthik T. Sundararajan, Timothy M. Jones, Nigel Topham

Research output: Chapter in Book/Report/Conference proceedingConference contribution


On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.
Original languageEnglish
Title of host publicationProceedings of the 8th ACM International Conference on Computing Frontiers
Place of PublicationNew York, NY, USA
Number of pages2
Publication statusPublished - 2011

Publication series

NameCF '11


  • cache tuning, configurable cache, smart cache


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