A Reconfigurable Cache Architecture for Energy Efficiency

Karthik T. Sundararajan; Timothy M. Jones; Nigel Topham

doi:10.1145/2016604.2016616

A Reconfigurable Cache Architecture for Energy Efficiency

Karthik T. Sundararajan, Timothy M. Jones, Nigel Topham

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.

Original language	English
Title of host publication	Proceedings of the 8th ACM International Conference on Computing Frontiers
Place of Publication	New York, NY, USA
Publisher	ACM
Pages	9:1-9:2
Number of pages	2
DOIs	https://doi.org/10.1145/2016604.2016616
Publication status	Published - 2011

Publication series

Name	CF '11
Publisher	ACM

Keywords / Materials (for Non-textual outputs)

cache tuning, configurable cache, smart cache

Access to Document

10.1145/2016604.2016616

http://doi.acm.org/10.1145/2016604.2016616

Dynamic Adaptation in Hetrogeneous Multicore Embedded Processors
Haas, H. (Principal Investigator), Franke, B. (Co-investigator), O'Boyle, M. (Co-investigator) & Topham, N. (Co-investigator)
EPSRC
1/11/10 → 30/07/14
Project: Research

Cite this

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title = "A Reconfigurable Cache Architecture for Energy Efficiency",

abstract = "On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18\% better than state-of-the-art reconfiguration architectures.",

keywords = "cache tuning, configurable cache, smart cache",

author = "Sundararajan, \{Karthik T.\} and Jones, \{Timothy M.\} and Nigel Topham",

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doi = "10.1145/2016604.2016616",

language = "English",

series = "CF '11",

publisher = "ACM",

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AU - Sundararajan, Karthik T.

AU - Jones, Timothy M.

AU - Topham, Nigel

PY - 2011

Y1 - 2011

N2 - On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.

AB - On-chip caches often consume a significant fraction of the total processor energy budget. Allowing adaptation to the running workload can significantly lower their energy consumption. In this paper, we present a novel Set and way Management cache Architecture for efficient Run-Time reconfiguration (Smart cache), a cache architecture that allows reconfiguration in both its size and associativity. Results show the energy-delay of the Smart cache is on average 18% better than state-of-the-art reconfiguration architectures.

KW - cache tuning, configurable cache, smart cache

U2 - 10.1145/2016604.2016616

DO - 10.1145/2016604.2016616

M3 - Conference contribution

T3 - CF '11

SP - 9:1-9:2

BT - Proceedings of the 8th ACM International Conference on Computing Frontiers

PB - ACM

CY - New York, NY, USA

ER -

A Reconfigurable Cache Architecture for Energy Efficiency

Abstract

Publication series

Keywords / Materials (for Non-textual outputs)

Access to Document

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Projects

Dynamic Adaptation in Hetrogeneous Multicore Embedded Processors

Cite this