A Reconfigurable Single-Photon-Counting Integrating Receiver for Optical Communications

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

A reconfigurable Single-Photon Avalanche Diode integrating receiver in standard 130nm CMOS is presented for optical links with an array readout bandwidth of 100MHz. A maximum count rate of 58GHz is observed, with SNR of 79dB, a sensitivity of -31.7dBm at 100MHz and a BER of 10−9. The sensor core draws 89mW at the maximum count rate. We investigate the properties of the receiver for optical communications in the visible spectrum. The all-digital 32x32 SPAD array achieves a minimum dead time of 5.9ns, and a median dark count rate of 2.5kHz per SPAD. The internal gain of SPADs and spatio-temporal summation removes the need for analogue amplification. High noise devices can be weighted or removed to optimise the SNR. Experimentally we explore the power requirements, transient response and received data to investigate the performance of such sensors, observing limiting factors similar to those for photodiode receivers.
Original languageEnglish
Pages (from-to)1-13
JournalIEEE Journal of Solid-State Circuits
Issue number7
Publication statusPublished - Jul 2013

Keywords / Materials (for Non-textual outputs)

  • visible light communications (VLCs)
  • single-photon avalanche diode (SPAD)
  • photon counting
  • OEIC
  • low-light receiver
  • interchip
  • integrating receiver
  • integrated
  • IEEE802.15.7
  • CMOS


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