A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Driver Development

Paul Daniel Judge; Ross Mathieson; Stephen J. Finney

A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Driver Development

Paul Daniel Judge, Ross Mathieson, Stephen J. Finney

School of Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper presents a new high-bandwidth multilevel gate-drive topology for use in Silicon Carbide (SiC) Active Gate-Driver Development. The presented Modular Multilevel gate Driver (MMGD) is a voltage modulated gate-driver topology that has a resolution of 2.5 ns and a current source/sink ability of approximately 5A, allowing for driving of high-power SiC MOSFETS. The MMGD is formed of off-the-shelf components, and so is readily reproducible. The speed of the gate-driver has been found to be fast enough to effectively PWM the gate of a high-power SiC MOSFET, allowing mutliple gate-driving strategies to be investigated. Experimental results using a 1.7 kV 300 A SiC MOSFET are given to validate the MMGDs ability to actively influence the switching behaviour of a high-power device.

Original language	English
Number of pages	7
Publication status	Published - 24 May 2021
Event	12th IEEE Energy Conversion Congress and Exposition - Asia, ECCE Asia 2021 - Virtual, Singapore, Singapore Duration: 24 May 2021 → 27 May 2021

Conference

Conference	12th IEEE Energy Conversion Congress and Exposition - Asia, ECCE Asia 2021
Country/Territory	Singapore
City	Virtual, Singapore
Period	24/05/21 → 27/05/21

Access to Document

output (2)Accepted author manuscript, 4.68 MB

1 Finished

Quietening ultra-low-loss SiC & GaN waveforms
Finney, S. & Djokic, S.
Engineering and Physical Sciences Research Council
1/06/18 → 30/09/23
Project: Research

1 Conference contribution

A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Drive Development
Judge, P. D., Mathieson, R. & Finney, S., 13 Jul 2021, (E-pub ahead of print) 2021 IEEE 12th Energy Conversion Congress & Exposition - Asia (ECCE-Asia). Institute of Electrical and Electronics Engineers, p. 2133-2138 6 p. 9479081. (International Conference on Power Electronics (ICPE) ; vol. 2021).
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Open Access

Cite this

@conference{c1fb53f145d34d74a4e891880ba8e658,

title = "A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Driver Development",

abstract = "This paper presents a new high-bandwidth multilevel gate-drive topology for use in Silicon Carbide (SiC) Active Gate-Driver Development. The presented Modular Multilevel gate Driver (MMGD) is a voltage modulated gate-driver topology that has a resolution of 2.5 ns and a current source/sink ability of approximately 5A, allowing for driving of high-power SiC MOSFETS. The MMGD is formed of off-the-shelf components, and so is readily reproducible. The speed of the gate-driver has been found to be fast enough to effectively PWM the gate of a high-power SiC MOSFET, allowing mutliple gate-driving strategies to be investigated. Experimental results using a 1.7 kV 300 A SiC MOSFET are given to validate the MMGDs ability to actively influence the switching behaviour of a high-power device.",

author = "Judge, {Paul Daniel} and Ross Mathieson and Finney, {Stephen J.}",

year = "2021",

month = may,

day = "24",

language = "English",

note = "12th IEEE Energy Conversion Congress and Exposition - Asia, ECCE Asia 2021 ; Conference date: 24-05-2021 Through 27-05-2021",

}

A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Driver Development. / Judge, Paul Daniel; Mathieson, Ross; Finney, Stephen J.
2021. Paper presented at 12th IEEE Energy Conversion Congress and Exposition - Asia, ECCE Asia 2021, Virtual, Singapore, Singapore.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Driver Development

AU - Judge, Paul Daniel

AU - Mathieson, Ross

AU - Finney, Stephen J.

PY - 2021/5/24

Y1 - 2021/5/24

N2 - This paper presents a new high-bandwidth multilevel gate-drive topology for use in Silicon Carbide (SiC) Active Gate-Driver Development. The presented Modular Multilevel gate Driver (MMGD) is a voltage modulated gate-driver topology that has a resolution of 2.5 ns and a current source/sink ability of approximately 5A, allowing for driving of high-power SiC MOSFETS. The MMGD is formed of off-the-shelf components, and so is readily reproducible. The speed of the gate-driver has been found to be fast enough to effectively PWM the gate of a high-power SiC MOSFET, allowing mutliple gate-driving strategies to be investigated. Experimental results using a 1.7 kV 300 A SiC MOSFET are given to validate the MMGDs ability to actively influence the switching behaviour of a high-power device.

AB - This paper presents a new high-bandwidth multilevel gate-drive topology for use in Silicon Carbide (SiC) Active Gate-Driver Development. The presented Modular Multilevel gate Driver (MMGD) is a voltage modulated gate-driver topology that has a resolution of 2.5 ns and a current source/sink ability of approximately 5A, allowing for driving of high-power SiC MOSFETS. The MMGD is formed of off-the-shelf components, and so is readily reproducible. The speed of the gate-driver has been found to be fast enough to effectively PWM the gate of a high-power SiC MOSFET, allowing mutliple gate-driving strategies to be investigated. Experimental results using a 1.7 kV 300 A SiC MOSFET are given to validate the MMGDs ability to actively influence the switching behaviour of a high-power device.

M3 - Paper

T2 - 12th IEEE Energy Conversion Congress and Exposition - Asia, ECCE Asia 2021

Y2 - 24 May 2021 through 27 May 2021

ER -

A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Driver Development

Abstract

Conference

Access to Document

Fingerprint

Projects

Quietening ultra-low-loss SiC & GaN waveforms

Research output

A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Drive Development

Cite this