Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator

Nick Brown; Ryan Barton

Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract / Description of output

The RISC-V Instruction Set Architecture (ISA) has enjoyed phenomenal growth in recent years, however it still to gain popularity in HPC. Whilst adopting RISC-V CPU solutions in HPC might be some way off, RISC-V based PCIe accelerators offer a middle ground where vendors benefit from the flexibility of RISC-V yet fit into existing systems.
In this paper we focus on the Tenstorrent Grayskull PCIe RISC-V based accelerator which, built upon Tensix cores, decouples data movement from compute. Using the Jacobi iterative method as a vehicle, we explore the suitability of stencils on the Grayskull e150. We explore best practice in structuring these codes for the accelerator and demonstrate that the e150 provides similar performance to a Xeon Platinum CPU (albeit BF16 vs FP32) but the e150 uses around five times less energy. Over four e150s we obtain around four times the CPU performance, again at around five times less energy.

Original language	English
Title of host publication	Proceedings of the International workshop on RISC-V for HPC
Publisher	IEEE Computer Society Press
Publication status	Accepted/In press - 1 Oct 2024
Event	International workshop on RISC-V for HPC (RISCV-HPC) at SC24 - Atlanta, United States Duration: 18 Nov 2024 → … https://riscv.epcc.ed.ac.uk/community/workshops/sc24-workshop/

Workshop

Workshop	International workshop on RISC-V for HPC (RISCV-HPC) at SC24
Abbreviated title	RISCV-HPC
Country/Territory	United States
City	Atlanta
Period	18/11/24 → …
Internet address	https://riscv.epcc.ed.ac.uk/community/workshops/sc24-workshop/

Access to Document

RISCV24_e150_aaAccepted author manuscript, 254 KBLicence: Creative Commons: Attribution (CC-BY)

https://arxiv.org/pdf/2409.18835Licence: Creative Commons: Attribution (CC-BY)

1 Finished
1 Active

EXCALIBURE H&ES RISC-V 2
Brown, N.
Engineering and Physical Sciences Research Council
1/04/23 → 28/02/25
Project: Research
ExCALIBUR H&ES RISC-V testbed
Brown, N.
Science and Technology Facilities Council
1/04/22 → 1/12/23
Project: Research

Cite this

@inproceedings{94ad93d3061e44bea2a0997f34989e6a,

title = "Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator",

abstract = "The RISC-V Instruction Set Architecture (ISA) has enjoyed phenomenal growth in recent years, however it still to gain popularity in HPC. Whilst adopting RISC-V CPU solutions in HPC might be some way off, RISC-V based PCIe accelerators offer a middle ground where vendors benefit from the flexibility of RISC-V yet fit into existing systems.In this paper we focus on the Tenstorrent Grayskull PCIe RISC-V based accelerator which, built upon Tensix cores, decouples data movement from compute. Using the Jacobi iterative method as a vehicle, we explore the suitability of stencils on the Grayskull e150. We explore best practice in structuring these codes for the accelerator and demonstrate that the e150 provides similar performance to a Xeon Platinum CPU (albeit BF16 vs FP32) but the e150 uses around five times less energy. Over four e150s we obtain around four times the CPU performance, again at around five times less energy.",

author = "Nick Brown and Ryan Barton",

year = "2024",

month = oct,

day = "1",

language = "English",

booktitle = "Proceedings of the International workshop on RISC-V for HPC",

publisher = "IEEE Computer Society Press",

note = "International workshop on RISC-V for HPC (RISCV-HPC) at SC24, RISCV-HPC ; Conference date: 18-11-2024",

url = "https://riscv.epcc.ed.ac.uk/community/workshops/sc24-workshop/",

}

TY - GEN

T1 - Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator

AU - Brown, Nick

AU - Barton, Ryan

PY - 2024/10/1

Y1 - 2024/10/1

N2 - The RISC-V Instruction Set Architecture (ISA) has enjoyed phenomenal growth in recent years, however it still to gain popularity in HPC. Whilst adopting RISC-V CPU solutions in HPC might be some way off, RISC-V based PCIe accelerators offer a middle ground where vendors benefit from the flexibility of RISC-V yet fit into existing systems.In this paper we focus on the Tenstorrent Grayskull PCIe RISC-V based accelerator which, built upon Tensix cores, decouples data movement from compute. Using the Jacobi iterative method as a vehicle, we explore the suitability of stencils on the Grayskull e150. We explore best practice in structuring these codes for the accelerator and demonstrate that the e150 provides similar performance to a Xeon Platinum CPU (albeit BF16 vs FP32) but the e150 uses around five times less energy. Over four e150s we obtain around four times the CPU performance, again at around five times less energy.

AB - The RISC-V Instruction Set Architecture (ISA) has enjoyed phenomenal growth in recent years, however it still to gain popularity in HPC. Whilst adopting RISC-V CPU solutions in HPC might be some way off, RISC-V based PCIe accelerators offer a middle ground where vendors benefit from the flexibility of RISC-V yet fit into existing systems.In this paper we focus on the Tenstorrent Grayskull PCIe RISC-V based accelerator which, built upon Tensix cores, decouples data movement from compute. Using the Jacobi iterative method as a vehicle, we explore the suitability of stencils on the Grayskull e150. We explore best practice in structuring these codes for the accelerator and demonstrate that the e150 provides similar performance to a Xeon Platinum CPU (albeit BF16 vs FP32) but the e150 uses around five times less energy. Over four e150s we obtain around four times the CPU performance, again at around five times less energy.

M3 - Conference contribution

BT - Proceedings of the International workshop on RISC-V for HPC

PB - IEEE Computer Society Press

T2 - International workshop on RISC-V for HPC (RISCV-HPC) at SC24

Y2 - 18 November 2024

ER -

Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator

Abstract / Description of output

Workshop

Access to Document

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Projects

EXCALIBURE H&ES RISC-V 2

ExCALIBUR H&ES RISC-V testbed

Cite this