Allocating Lifetimes to Queues in Software Pipelined Architectures

Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Software pipelining is an effective technique for increasing the throughput of loops in superscalar or VLIW machines, however it generates high register pressure, which in some cases requires the introduction of spill code into the schedule. Large multi-ported register files present significant problems in the construction of scalable VLIW systems, which has lead us to investigate architectures in which part of the register file is replaced by queues. We believe that this organization has distinct advantages in terms of hardware complexity, silicon area, instruction name space, and scalability. Queues also represent a natural mechanism for communication between clusters of functional units in a partitioned VLIW system. In this paper we present an overview of this approach, along with some experimental results suggesting it as being a feasible organization.
Original languageEnglish
Title of host publicationEuro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings
PublisherSpringer Berlin Heidelberg
Pages1066-1073
Number of pages8
ISBN (Electronic)978-3-540-69549-3
ISBN (Print)978-3-540-63440-9
DOIs
Publication statusPublished - 1997

Publication series

NameLecture Notes in Computer Science
PublisherSpringer Berlin Heidelberg
ISSN (Print)0302-9743

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