TY - JOUR
T1 - An Asynchronous Spike Event Coding Scheme for Programmable Analog Arrays
AU - Gouveia, Luiz Carlos
AU - Koickal, Thomas Jacob
AU - Hamilton, Alister
PY - 2011/4
Y1 - 2011/4
N2 - This paper presents a spike time event coding scheme for transmission of analog signals between configurable analog blocks (CABs) in a programmable analog array. The analog signals from CABs are encoded as spike time instants dependent upon input signal activity and are transmitted asynchronously by employing the address event representation protocol (AER), a widely used communication protocol in neuromorphic systems. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. Computation is intrinsic to the spike event coding scheme and is performed without additional hardware. The ability of the communication scheme to perform computation will enhance the computation power of the programmable analog array. The design methodology and analog circuit design of the scheme are presented. Test results from prototype chips implemented using a 3.3-V, 0.35-mu m CMOS technology are presented.
AB - This paper presents a spike time event coding scheme for transmission of analog signals between configurable analog blocks (CABs) in a programmable analog array. The analog signals from CABs are encoded as spike time instants dependent upon input signal activity and are transmitted asynchronously by employing the address event representation protocol (AER), a widely used communication protocol in neuromorphic systems. Power dissipation is dependent upon input signal activity and no spike events are generated when the input signal is constant. Computation is intrinsic to the spike event coding scheme and is performed without additional hardware. The ability of the communication scheme to perform computation will enhance the computation power of the programmable analog array. The design methodology and analog circuit design of the scheme are presented. Test results from prototype chips implemented using a 3.3-V, 0.35-mu m CMOS technology are presented.
UR - http://www.scopus.com/inward/record.url?scp=79953278182&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2010.2089552
DO - 10.1109/TCSI.2010.2089552
M3 - Article
SN - 1549-8328
VL - 58
SP - 791
EP - 799
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 4
ER -