An efficient hardware architecture for multilayer spiking neural networks

Yuling Luo, Lei Wan, Junxiu Liu*, Jinlei Zhang, Yi Cao

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visualization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hardware system. Experimental results demonstrate that the proposed architecture is feasible and capable of scaling to large hardware multilayer SNNs.

Original languageEnglish
Title of host publicationNeural Information Processing - 24th International Conference, ICONIP 2017, Proceedings
EditorsDerong Liu, Shengli Xie, Dongbin Zhao, Yuanqing Li, El-Sayed M. El-Alfy
PublisherSpringer-Verlag
Pages786-795
Number of pages10
ISBN (Print)9783319701356
DOIs
Publication statusPublished - 2017
Event24th International Conference on Neural Information Processing, ICONIP 2017 - Guangzhou, China
Duration: 14 Nov 201718 Nov 2017

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume10639 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference24th International Conference on Neural Information Processing, ICONIP 2017
Country/TerritoryChina
CityGuangzhou
Period14/11/1718/11/17

Keywords

  • FPGA
  • hardware architecture
  • spiking neural networks

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