Many modern workloads compute on large amounts of data, often with irregular memory accesses. Current architectures perform poorly for these workloads, as existing prefetching techniques cannot capture the memory access patterns; these applications end up heavily memory-bound as a result. Although a number of techniques exist to explicitly configure a prefetcher with traversal patterns, gaining significant speedups, they do not generalise beyond their target data structures. Instead, we propose an event-triggered programmable prefetcher combining the flexibility of a general-purpose computational unit with an event-based programming model, along with compiler techniques to automatically generate events from the original source code with annotations. This allows more complex fetching decisions to be made, without needing to stall when intermediate results are required. Using our programmable prefetching system, combined with small prefetch kernels extracted from applications, we achieve an average 3.0x speedup in simulation for a variety of graph, database and HPC workloads.
|Number of pages||15|
|Journal||ACM Sigplan Notices|
|Publication status||Published - 19 Mar 2018|
|Event||The 23rd ACM International Conference on Architectural Support for Programming Languages and Operating Systems - Williamsburg, United States|
Duration: 24 Mar 2018 → 28 Mar 2018
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- School of Informatics - Visitor: Staff Other UK HEI
Person: Affiliated Independent Researcher