Abstract
Current approaches for mapping Kahn Process Networks (KPN) and Dynamic Data Flow (DDF) applications rely on assumptions on the program behavior specific to an execution. Thus, a near-optimal mapping, computed for a given input data set, may become sub-optimal at run-time. This happens when a different data set induces a significantly different behavior. We address this problem by leveraging inherent mathematical structures of the dataflow models and the hardware architectures. On the side of the dataflow models, we rely on the monoid structure of histories and traces. This structure help us formalize the behavior of multiple executions of a given dynamic application. By defining metrics we have a formal framework for comparing the executions. On the side of the hardware, we take advantage of symmetries in the architecture to reduce the search space for the mapping problem. We evaluate our implementation on execution variations of a randomly-generated KPN application and on a low-variation JPEG encoder benchmark. Using the described methods we show that trace differences are not sufficient for characterizing performance losses. Additionally, using platform symmetries we manage to reduce the design space in the experiments by two orders of magnitude.
Original language | English |
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Title of host publication | System Level Design from HW/SW to Memory for Embedded Systems |
Editors | Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, Achim Rettberg |
Place of Publication | Cham |
Publisher | Springer |
Pages | 116-127 |
Number of pages | 12 |
ISBN (Electronic) | 978-3-319-90023-0 |
DOIs | |
Publication status | Published - 17 Apr 2018 |
Event | International Embedded Systems Symposium 2015 - Foz do Iguacu, Brazil Duration: 3 Nov 2015 → 6 Nov 2015 |
Conference
Conference | International Embedded Systems Symposium 2015 |
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Abbreviated title | IESS 2015 |
Country/Territory | Brazil |
City | Foz do Iguacu |
Period | 3/11/15 → 6/11/15 |