Architecture and design methodology for synthesizable reconfigurable array targeting wireless system-on-chip applications

C Zhan, S Khawam, T Arslan, Iain Lindsay

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a novel domain specific reconfigurable architecture and an associate design methodology for System-on-Chip (SoC) platform which provides flexibility as well as low-power consumption. Two Viterbi decoders, which are widely used in wireless communication system, are implemented on the proposed architecture using the proposed design methodology. The measured performance shows that our architecture is a perfect compromise between the ASICs and generic FPGAs, and hence suitable for future portable mobile devices.

Original languageEnglish
Title of host publicationIEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS
EditorsD Ha, R Krishnamurthy, S Kim, A Marshall
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages93-94
Number of pages2
ISBN (Print)0-7803-9264-7
Publication statusPublished - 2005
EventIEEE International SOC Conference - Herndon
Duration: 25 Sep 200528 Sep 2005

Conference

ConferenceIEEE International SOC Conference
CityHerndon
Period25/09/0528/09/05

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