Architecture for microprocessor-based systems including simd processing unit and associated systems and methods

Kar-Lik Wong; Carl Graham; Nigel Topham; Simon Jones; Aris Aristodemou; Yazid Nemouchi; Seow Chuan Lim

Architecture for microprocessor-based systems including simd processing unit and associated systems and methods

Kar-Lik Wong (Inventor), Carl Graham (Inventor), Nigel Topham (Inventor), Simon Jones (Inventor), Aris Aristodemou (Inventor), Yazid Nemouchi (Inventor), Seow Chuan Lim (Inventor)

Research output: Patent

Abstract

An architecture for microprocessor-based systems is provided. The architecture includes a SIMD processing unit and associated systems and methods for optimizing the performance of such a system. In one embodiment systems and methods for performing systolic array-based block matching are provided. In another embodiment, a parameterizable clip instruction is provided. In an additional embodiment, two pair of deblocking instruction for use with the H.264 and VCl codecs provided. In a further embodiment, an instruction and datapath for accelerating sub-pixel interpolation are provided. In another embodiment, systems and methods for selectively decoupling processor extension logic are provided. In yet another embodiment, systems and methods for recording instruction sequences in a microprocessor having dynamically decoupleable extension logic is provided, hi yet one other embodiment, systems and methods for synchronizing multiple processing engines of a SIMD engine are provided.

Original language	English
IPC	WO 2007049150
Priority date	28/09/05
Publication status	Published - 2007

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@misc{301647dff4794e5b986b97abbbf5017b,

title = "Architecture for microprocessor-based systems including simd processing unit and associated systems and methods",

abstract = "An architecture for microprocessor-based systems is provided. The architecture includes a SIMD processing unit and associated systems and methods for optimizing the performance of such a system. In one embodiment systems and methods for performing systolic array-based block matching are provided. In another embodiment, a parameterizable clip instruction is provided. In an additional embodiment, two pair of deblocking instruction for use with the H.264 and VCl codecs provided. In a further embodiment, an instruction and datapath for accelerating sub-pixel interpolation are provided. In another embodiment, systems and methods for selectively decoupling processor extension logic are provided. In yet another embodiment, systems and methods for recording instruction sequences in a microprocessor having dynamically decoupleable extension logic is provided, hi yet one other embodiment, systems and methods for synchronizing multiple processing engines of a SIMD engine are provided.",

author = "Kar-Lik Wong and Carl Graham and Nigel Topham and Simon Jones and Aris Aristodemou and Yazid Nemouchi and Lim, {Seow Chuan}",

year = "2007",

language = "English",

type = "Patent",

note = "WO 2007049150",

}

TY - PAT

T1 - Architecture for microprocessor-based systems including simd processing unit and associated systems and methods

AU - Wong, Kar-Lik

AU - Graham, Carl

AU - Topham, Nigel

AU - Jones, Simon

AU - Aristodemou, Aris

AU - Nemouchi, Yazid

AU - Lim, Seow Chuan

PY - 2007

Y1 - 2007

N2 - An architecture for microprocessor-based systems is provided. The architecture includes a SIMD processing unit and associated systems and methods for optimizing the performance of such a system. In one embodiment systems and methods for performing systolic array-based block matching are provided. In another embodiment, a parameterizable clip instruction is provided. In an additional embodiment, two pair of deblocking instruction for use with the H.264 and VCl codecs provided. In a further embodiment, an instruction and datapath for accelerating sub-pixel interpolation are provided. In another embodiment, systems and methods for selectively decoupling processor extension logic are provided. In yet another embodiment, systems and methods for recording instruction sequences in a microprocessor having dynamically decoupleable extension logic is provided, hi yet one other embodiment, systems and methods for synchronizing multiple processing engines of a SIMD engine are provided.

AB - An architecture for microprocessor-based systems is provided. The architecture includes a SIMD processing unit and associated systems and methods for optimizing the performance of such a system. In one embodiment systems and methods for performing systolic array-based block matching are provided. In another embodiment, a parameterizable clip instruction is provided. In an additional embodiment, two pair of deblocking instruction for use with the H.264 and VCl codecs provided. In a further embodiment, an instruction and datapath for accelerating sub-pixel interpolation are provided. In another embodiment, systems and methods for selectively decoupling processor extension logic are provided. In yet another embodiment, systems and methods for recording instruction sequences in a microprocessor having dynamically decoupleable extension logic is provided, hi yet one other embodiment, systems and methods for synchronizing multiple processing engines of a SIMD engine are provided.

M3 - Patent

ER -