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The novel overlay test structure reported in this paper was purposely designed to serve as an application-specific reference material. It features standard frame-in-frame optical overlay targets embedded in electrical test features and fabricated by the same process as the parts being manufactured. Optical overlay is commonly used in process control applications due to its utility for determining the relative positions of features patterned in photoresist. Electrical overlay, although it can only be measured on fully patterned test structures, is the metric of interest. Using this combined optical/electrical overlay test structure, we can derive the relationship between the routinely measured optical overlay and the electrical overlay for any specific combination of process and optical overlay tool.
|Title of host publication||2007 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, PROCEEDINGS|
|Place of Publication||NEW YORK|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||6|
|Publication status||Published - 2007|
|Event||IEEE International Conference on Microelectronic Test Structures - Tokyo|
Duration: 19 Mar 2007 → 22 Mar 2007
|Conference||IEEE International Conference on Microelectronic Test Structures|
|Period||19/03/07 → 22/03/07|
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- 1 Finished
Optimisation of sub-100nm copper-interconnect and photoresist tracks for high density IC fabrication metrology
1/01/05 → 30/06/06