Array-processor Architecture

R. N. Ibbett; N. P. Topham

doi:10.1007/978-1-4899-6701-5_2

Array-processor Architecture

R. N. Ibbett, N. P. Topham

School of Informatics

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units. In such machines the link between the two parts creates a bottleneck, defining an upper-bound on performance. Furthermore, this two-part design produces extremely inefficient architectures when the metric of efficiency is the utilisation of individual switching elements.

Original language	English
Title of host publication	Architecture of High Performance Computers Volume II
Subtitle of host publication	Array processors and multiprocessor systems
Place of Publication	New York, NY
Publisher	Springer New York
Pages	6-21
Number of pages	16
ISBN (Electronic)	978-1-4899-6701-5
ISBN (Print)	978-1-4899-6703-9
DOIs	https://doi.org/10.1007/978-1-4899-6701-5_2
Publication status	Published - 1989

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@inbook{78c636b0d08a47c4996893291bf987ef,

title = "Array-processor Architecture",

abstract = "In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units. In such machines the link between the two parts creates a bottleneck, defining an upper-bound on performance. Furthermore, this two-part design produces extremely inefficient architectures when the metric of efficiency is the utilisation of individual switching elements.",

author = "Ibbett, {R. N.} and Topham, {N. P.}",

year = "1989",

doi = "10.1007/978-1-4899-6701-5_2",

language = "English",

isbn = " 978-1-4899-6703-9",

pages = "6--21",

booktitle = "Architecture of High Performance Computers Volume II",

publisher = "Springer New York",

address = "United States",

}

TY - CHAP

T1 - Array-processor Architecture

AU - Ibbett, R. N.

AU - Topham, N. P.

PY - 1989

Y1 - 1989

N2 - In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units. In such machines the link between the two parts creates a bottleneck, defining an upper-bound on performance. Furthermore, this two-part design produces extremely inefficient architectures when the metric of efficiency is the utilisation of individual switching elements.

AB - In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units. In such machines the link between the two parts creates a bottleneck, defining an upper-bound on performance. Furthermore, this two-part design produces extremely inefficient architectures when the metric of efficiency is the utilisation of individual switching elements.

U2 - 10.1007/978-1-4899-6701-5_2

DO - 10.1007/978-1-4899-6701-5_2

M3 - Chapter

SN - 978-1-4899-6703-9

SP - 6

EP - 21

BT - Architecture of High Performance Computers Volume II

PB - Springer New York

CY - New York, NY

ER -

Array-processor Architecture

Abstract

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