Array-processor Architecture

R. N. Ibbett, N. P. Topham

Research output: Chapter in Book/Report/Conference proceedingChapter


In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units. In such machines the link between the two parts creates a bottleneck, defining an upper-bound on performance. Furthermore, this two-part design produces extremely inefficient architectures when the metric of efficiency is the utilisation of individual switching elements.
Original languageEnglish
Title of host publicationArchitecture of High Performance Computers Volume II
Subtitle of host publicationArray processors and multiprocessor systems
Place of PublicationNew York, NY
PublisherSpringer New York
Number of pages16
ISBN (Electronic)978-1-4899-6701-5
ISBN (Print) 978-1-4899-6703-9
Publication statusPublished - 1989


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