Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Tarek Al abbas; Neale Dutton; Oscar Almer; Sara Pellegrini; Y. Henrion; Robert Henderson

doi:10.1109/IEDM.2016.7838372

Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Tarek Al abbas, Neale Dutton, Oscar Almer, Sara Pellegrini, Y. Henrion, Robert Henderson

School of Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract / Description of output

We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3 V excess bias.

Original language	English
Number of pages	4
DOIs	https://doi.org/10.1109/IEDM.2016.7838372
Publication status	Published - 3 Dec 2016
Event	International Electron Devices Meeting - San Francisco, United States Duration: 3 Dec 2016 → 6 Dec 2016

Conference

Conference	International Electron Devices Meeting
Country/Territory	United States
City	San Francisco
Period	3/12/16 → 6/12/16

Access to Document

10.1109/IEDM.2016.7838372

AbbasIEDM2016Submitted

Multiplexed 'Touch and Tell' Optical Molecular Sensing and Imaging
Henderson, R.
EPSRC
1/10/13 → 31/03/19
Project: Research
PhD Student Support- as part of the UoE/STMicroelectronic Research Collaboration
Henderson, R.
UK industry, commerce and public corporations
1/01/11 → 29/02/20
Project: Research

Cite this

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title = "Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology",

abstract = "We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3 V excess bias.",

author = "{Al abbas}, Tarek and Neale Dutton and Oscar Almer and Sara Pellegrini and Y. Henrion and Robert Henderson",

year = "2016",

month = dec,

day = "3",

doi = "10.1109/IEDM.2016.7838372",

language = "English",

note = "International Electron Devices Meeting ; Conference date: 03-12-2016 Through 06-12-2016",

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T1 - Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

AU - Al abbas, Tarek

AU - Dutton, Neale

AU - Almer, Oscar

AU - Pellegrini, Sara

AU - Henrion, Y.

AU - Henderson, Robert

PY - 2016/12/3

Y1 - 2016/12/3

N2 - We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3 V excess bias.

AB - We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3 V excess bias.

U2 - 10.1109/IEDM.2016.7838372

DO - 10.1109/IEDM.2016.7838372

M3 - Paper

T2 - International Electron Devices Meeting

Y2 - 3 December 2016 through 6 December 2016

ER -

Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

Abstract / Description of output

Conference

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Projects

Multiplexed 'Touch and Tell' Optical Molecular Sensing and Imaging

PhD Student Support- as part of the UoE/STMicroelectronic Research Collaboration

Cite this