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Abstract / Description of output
Specialized hardware accelerators continue to be a source of performance improvement. However, such specialization comes at a programming price. The fundamental issue is that of a mismatch between the diversity of user code and the functionality of fixed hardware, limiting its wider uptake. Here we focus on a particular set of accelerators: those for Fast Fourier Transforms. We present FACC (Fourier ACcelerator Compiler), a novel approach to automatically map legacy code to Fourier Transform accelerators. It automatically generates drop-in replacement adapters using InputOutput (IO)-based program synthesis that bridge the gap between user code and accelerators. We apply FACC to unmodified GitHub C programs of varying complexity and compare against two existing approaches. We target FACC to a high-performance library, FFTW, and two hardware accelerators, the NXP PowerQuad and the Analog Devices FFTA, and demonstrate mean speedups of 9x, 17x and 27x respectively.
Original language | English |
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Title of host publication | Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation |
Editors | Ranjit Jhala, Işil Dillig |
Publisher | ACM |
Pages | 687-702 |
Number of pages | 16 |
ISBN (Print) | 978-1-4503-9265-5 |
DOIs | |
Publication status | Published - 9 Jun 2022 |
Event | 43rd ACM SIGPLAN Conference on Programming Language Design and Implementation - San Diego, United States Duration: 15 Jun 2022 → 17 Jun 2022 Conference number: 43 https://pldi22.sigplan.org/ |
Conference
Conference | 43rd ACM SIGPLAN Conference on Programming Language Design and Implementation |
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Abbreviated title | PLDI 2022 |
Country/Territory | United States |
City | San Diego |
Period | 15/06/22 → 17/06/22 |
Internet address |
Keywords / Materials (for Non-textual outputs)
- Hardware Accelerators
- Program Synthesis
- FFT
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