BIST for strongly-indicating asynchronous circuits

D. Koppad, A. Efthymiou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Testing asynchronous circuits is difficult and is one of the main reasons why these circuits are not very popular. This paper explores a test methodology for quasi-delay-insensitive circuits. It is shown that the test method proposed achieves 100% fault coverage for single stuck-at faults and also results in saving nearly 150% area overhead compared to the LSSD test approach. The method has been automated and fault coverage analysis has been performed on the ISCAS-85 benchmarks using Verifault-XL.
Original languageEnglish
Title of host publicationVery Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on
Number of pages4
Publication statusPublished - 1 Oct 2009


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