BIST for strongly-indicating asynchronous circuits

D. Koppad; A. Efthymiou

doi:10.1109/VLSISOC.2009.6041359

BIST for strongly-indicating asynchronous circuits

D. Koppad, A. Efthymiou

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Testing asynchronous circuits is difficult and is one of the main reasons why these circuits are not very popular. This paper explores a test methodology for quasi-delay-insensitive circuits. It is shown that the test method proposed achieves 100% fault coverage for single stuck-at faults and also results in saving nearly 150% area overhead compared to the LSSD test approach. The method has been automated and fault coverage analysis has been performed on the ISCAS-85 benchmarks using Verifault-XL.

Original language	English
Title of host publication	Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on
Pages	215-218
Number of pages	4
DOIs	https://doi.org/10.1109/VLSISOC.2009.6041359
Publication status	Published - 1 Oct 2009

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10.1109/VLSISOC.2009.6041359

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title = "BIST for strongly-indicating asynchronous circuits",

abstract = "Testing asynchronous circuits is difficult and is one of the main reasons why these circuits are not very popular. This paper explores a test methodology for quasi-delay-insensitive circuits. It is shown that the test method proposed achieves 100\% fault coverage for single stuck-at faults and also results in saving nearly 150\% area overhead compared to the LSSD test approach. The method has been automated and fault coverage analysis has been performed on the ISCAS-85 benchmarks using Verifault-XL.",

author = "D. Koppad and A. Efthymiou",

year = "2009",

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doi = "10.1109/VLSISOC.2009.6041359",

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AU - Efthymiou, A.

PY - 2009/10/1

Y1 - 2009/10/1

N2 - Testing asynchronous circuits is difficult and is one of the main reasons why these circuits are not very popular. This paper explores a test methodology for quasi-delay-insensitive circuits. It is shown that the test method proposed achieves 100% fault coverage for single stuck-at faults and also results in saving nearly 150% area overhead compared to the LSSD test approach. The method has been automated and fault coverage analysis has been performed on the ISCAS-85 benchmarks using Verifault-XL.

AB - Testing asynchronous circuits is difficult and is one of the main reasons why these circuits are not very popular. This paper explores a test methodology for quasi-delay-insensitive circuits. It is shown that the test method proposed achieves 100% fault coverage for single stuck-at faults and also results in saving nearly 150% area overhead compared to the LSSD test approach. The method has been automated and fault coverage analysis has been performed on the ISCAS-85 benchmarks using Verifault-XL.

U2 - 10.1109/VLSISOC.2009.6041359

DO - 10.1109/VLSISOC.2009.6041359

M3 - Conference contribution

SN - 978-1-4577-0237-2

SP - 215

EP - 218

BT - Very Large Scale Integration (VLSI-SoC), 2009 17th IFIP International Conference on

ER -

BIST for strongly-indicating asynchronous circuits

Abstract

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