Boomerang: a Metadata-Free Architecture for Control Flow Delivery

Rakesh Kumar, Cheng-Chieh Huang, Boris Grot, Vijayanand Nagarajan

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Contemporary server workloads feature massive instruction footprints stemming from deep, layered software stacks. The active instruction working set of the entire stack can easily reach into megabytes, resulting in frequent frontend
stalls due to instruction cache misses and pipeline flushes due to branch target buffer (BTB) misses. While a number of techniques have been proposed to address these problems, every one of them requires dedicated metadata structures, translating into significant storage and complexity costs.
In this paper, we ask the question whether it is possible to achieve high-performance control flow delivery without the metadata costs of prior techniques. We revisit a previously proposed approach of branch-predictor-directed prefetching, which leverages just the branch predictor and BTB to discover and prefetch the missing instruction cache blocks by exploring the
program control flow ahead of the core front-end. Contrary to conventional wisdom, we find that this approach can be effective in covering instruction cache misses in modern CMPs with long LLC access latencies and multi-MB server binaries. Our first contribution lies in explaining the reasons for the efficacy of branch-predictor-directed prefetching. Our second contribution is in Boomerang, a metadata-free architecture for control flow delivery. Boomerang leverages a branch-predictor directed prefetcher to discover and prefill not only the instruction cache blocks, but also the missing BTB entries. Crucially, we
demonstrate that the additional hardware cost required to identify and fill BTB misses is negligible. Our experimental evaluation shows that Boomerang matches the performance of the state-of-the-art control flow delivery scheme without the latter’s high metadata and complexity overheads.
Original languageEnglish
Title of host publicationThe 23rd IEEE International Symposium on High-Performance Computer Architecture
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages12
ISBN (Print)978-1-5090-4985-1
Publication statusPublished - 8 May 2017
Event23rd IEEE International Symposium on High-Performance Computer Architecture - Austin, United States
Duration: 4 Feb 20178 Feb 2017

Publication series

ISSN (Electronic)2378-203X


Conference23rd IEEE International Symposium on High-Performance Computer Architecture
Abbreviated titleHPCA 2017
Country/TerritoryUnited States
Internet address


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