Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms

Maximilian Odendahl, Andrés Goens, Rainer Leupers, Gerd Ascheid, Tomas Henriksson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The problem of finding an optimal allocation of logical data buffers to memory has emerged as a new research challenge due to the increased complexity of applications and new emerging Dynamic RAM (DRAM) interface technologies. This new opportunity of a large off-chip memory accessible by an ample bandwidth allows to reduce the on-chip Static RAM (SRAM) significantly and save production cost of future manycore platforms. We thus propose changes to an existing work that allows to uniformly reduce the on-chip memory size for a given application. We additionally introduce a novel linear programming model to automatically generate all necessary on chip memory sizes for a given application based on an optimal allocation of data buffers. An extension allows to further reduce the required on-chip memory in multi-application scenarios. We conduct a case study to validate all our models and show the applicability of our approach.
Original languageEnglish
Title of host publication2015 IEEE International Parallel and Distributed Processing Symposium Workshop
PublisherInstitute of Electrical and Electronics Engineers
Pages1119-1124
Number of pages6
ISBN (Electronic)978-1-4673-7684-6
DOIs
Publication statusPublished - 1 Oct 2015
Event36th IEEE International Parallel and Distributed Processing Symposium - Hyderabad, India
Duration: 25 May 201529 May 2015

Conference

Conference36th IEEE International Parallel and Distributed Processing Symposium
Abbreviated titleIPDPS 2015
Country/TerritoryIndia
CityHyderabad
Period25/05/1529/05/15

Keywords / Materials (for Non-textual outputs)

  • mapping
  • exploration
  • optimization
  • many-core
  • mpsoc

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