Abstract
Several cache management techniques have been proposed that indirectly try to base their decisions on cacheline reuse-distance, like Cache Decay which is a postdiction of reuse-distances: if a cacheline has not been accessed for some ldquodecay intervalrdquo we know that its reuse-distance is at least as large as this decay interval. In this work, we propose to directly predict reuse-distances via instruction-based (PC) prediction and use this information for cache level optimizations. In this paper, we choose as our target for optimization the replacement policy of the L2 cache, because the gap between the LRU and the theoretical optimal replacement algorithm is comparatively large for L2 caches. This indicates that, in many situations, there is ample room for improvement. We evaluate our reusedistance based replacement policy using a subset of the most memory intensive SPEC2000 and our results show significant benefits across the board.
Original language | English |
---|---|
Title of host publication | Computer Design, 2007. ICCD 2007. 25th International Conference on |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 245-250 |
Number of pages | 6 |
ISBN (Print) | 978-1-4244-1257-0 |
DOIs | |
Publication status | Published - 1 Oct 2007 |