Characterization of Clock Buffers for On-Chip Inter-Circuit Communication in Xilinx FPGAs

Adewale Adetomi, Godwin Enemali, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Resource underutilization can occur in FPGAs if there is not enough routing resource to connect circuit elements in a region of the chip area. To alleviate this, we have proposed the use of clock buffers for on-chip data routing. Moreover, dynamism in communication for reliability is facilitated by using clock buffers for communication. This is because the clock routing network is independent of the general interconnect. In this paper, we present different configurations of the clock buffers in a Xilinx 7 series FPGA and characterize them based on the achievable speed of communication.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538648810
DOIs
Publication statusPublished - 26 Apr 2018
Event2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Florence, Italy
Duration: 27 May 201830 May 2018

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2018-May
ISSN (Print)0271-4310

Conference

Conference2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018
CountryItaly
CityFlorence
Period27/05/1830/05/18

Keywords

  • CELOC
  • clock buffers
  • network on chip
  • NoC link
  • on-chip communication

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