ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality

Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, Onur Mutlu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism,called ChargeCache, that enables faster access to recently accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation,we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rrows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides signicant performance and energy benefits for both single-core and multi-core systems.
Original languageEnglish
Title of host publication2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages581-593
Number of pages13
ISBN (Print)978-1-4673-9211-2
DOIs
Publication statusPublished - Mar 2016
Event2016 IEEE International Symposium on High Performance Computer Architecture - Barcelona, Spain
Duration: 12 Mar 201616 Mar 2016
http://hpca22.site.ac.upc.edu/

Conference

Conference2016 IEEE International Symposium on High Performance Computer Architecture
Abbreviated titleHPCA 2016
CountrySpain
CityBarcelona
Period12/03/1616/03/16
Internet address

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